I am reading about SDRAM, and how the bandwidth was increased with DDR optimizations. From my understanding DDR can send data at a rising and falling edge, effectively doubling the data being sent. But how is this implemented at the level of a memory array without increasing its operating frequency?
I suspect that a memory array multiplexer would have 2 output lines, and when selecting a column, it is automatically selecting 2 cells in the memory array. Then another buffer would be responsible for detecting the rising and falling edges, forwarding each output pin from the multiplexer individually to the data bus.
I haven't really been able to find anything online that backs my reasoning, so any pointers would be great.