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I am reading about SDRAM, and how the bandwidth was increased with DDR optimizations. From my understanding DDR can send data at a rising and falling edge, effectively doubling the data being sent. But how is this implemented at the level of a memory array without increasing its operating frequency?

I suspect that a memory array multiplexer would have 2 output lines, and when selecting a column, it is automatically selecting 2 cells in the memory array. Then another buffer would be responsible for detecting the rising and falling edges, forwarding each output pin from the multiplexer individually to the data bus.

I haven't really been able to find anything online that backs my reasoning, so any pointers would be great.

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  • \$\begingroup\$ Internally, the memory array is accessed an entire row at a time, in parallel. Then the question becomes, how fast can you multiplex all those bits through the available I/O pins? \$\endgroup\$
    – Dave Tweed
    Commented Mar 18, 2023 at 16:18
  • \$\begingroup\$ So after a row has been selected, whatever selects the column has to select as many columns as the burst length at different time intervals? From this figure link my interpretation is that for DDR2, the array outputs 4 bits, and the buffer would then select the bit based on the clock rising and falling edge. \$\endgroup\$ Commented Mar 19, 2023 at 12:04

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It's not the frequency that the memory cells operates, they don't even have a clock.

It's the bus interface. You define the bus interface and transfer data through the memory via the interface.

It is completely different and irrelevant how the memory works internally as long as it can be accessed through the interface.

What matters is that if the bus can transfer 200 megatransactions per second, the memory chips need to handle that. If the bus requires a 200 MHz or 100 MHz or some other clock to do that, it's just the reference clock used for the bus, and what the memory chip does with that bus reference clock is up to implementation.

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  • \$\begingroup\$ Thank you for your reply. But at some point, a row and column have to be selected. What I still can't understand is whether all bits that an array will send in a single burst are selected at once, or if multiple columns are selected at very short discrete time intervals by sending a new column address without changing the row address. \$\endgroup\$ Commented Mar 19, 2023 at 12:09
  • \$\begingroup\$ That's a completely different question then. Opening a row already latches all column data bits through the sense amplifiers to some temporary buffer, and this is a destructive operation to the data in memory cells. Then you can read and write the temporary buffer, and when you are finished with the row, you close the row and all column bits are written back from temporary buffer to memory cells. \$\endgroup\$
    – Justme
    Commented Mar 19, 2023 at 12:27
  • \$\begingroup\$ Sorry, this was the question I was trying to convery. So if I understood correctly, when a row is read, the whole row is placed into the sense amplifiers. Then a multiplexer has to select which of the values in the sense amplifiers is selected. How many values does the multiplexer return? In this figure (link) I get the idea the multiplexer in DDR2 would return 4 bit values for a single column address. \$\endgroup\$ Commented Mar 19, 2023 at 12:37

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