# How does a bootstrap circuit work and how can I calculate the resistor and capacitor values?

I am designing an H-bridge with an N-channel MOSFET to control a 12V - 1.35A DC motor. The H-bridge will be controlled with the digital outputs of an Arduino. I did some research and found that I need to use a bootstrap circuit, which from what I understood is to improve the linearity of the MOS switch (on resistance of transistor) by making sure that the signals from the source and the gate of the NFET follow each other. For this, a capacitor is added between the gate and the source of the transistor, so that the gate and source signals follow each other.

I found a bootstrap circuit and included it in the H-bridge design, but didn't end up understanding how the boostrap works.

• Where is the capacitor supposed to find its way to ground?
• How do I calculate the value of the boostrap resistor and capacitor?
• Is the circuit correct? It works in the simulator, but I don't know if it works in real life.
• When Q10 switches on C1 finds its way to ground. Why don't you use a proper bootstrap driver chip? Commented Mar 18, 2023 at 14:22
• @PeterJennings: An H-bridge can drive a DC motor in either direction. Add in PWM, and you have bi-directional motor speed control for a DC motor.
– JRE
Commented Mar 18, 2023 at 14:30
• @Andyaka Which bootstrap driver chip do you recommend? Commented Mar 18, 2023 at 14:35
• Besides a bootstrap voltage, you need a level shifter on the high-side switches. I don't see it. Commented Mar 18, 2023 at 14:35
• Please turn off the graph on your schematic. Commented Mar 18, 2023 at 14:58

The bootstrap circuit is needed when you use an N-channel MOSFET as a high-side switch. That's because the MOSFET is operating as a source follower (common drain), which means that source potential is always a few volts lower than gate potential. Obviously you need the source to rise all the way to the positive supply, so in order to get minimum on-resistance, you need to raise the gate several volts higher than the positive supply.

The principle is to charge a capacitor to the full supply potential (say 12V), and whenever you want the transistor "on", "insert" the capacitor into the path between the normal digital 12V gate drive signal, and the gate, so that the gate actually sees the sum of the digital signal and the capacitor's voltage, 12V + 12V = 24V.

You only want this to happen when the transistor is supposed to be on, because to switch that transistor off again requires that the gate be at 0V. In that case, you obviously don't want the capacitor's voltage to be added, so you have to somehow remove the capacitor from that path when the transistor is supposed to be off.

I can't see how the circuit that you provided in your question can do that. The switches pull up to +5V, which cannot possibly cause the bootstrap circuit to operate correctly. For it to work, those switches must pull down to ground, which requires other changes.

For instance, R18 in your circuit is supposed to pull down the gate to ground, but it can't possibly overcome the upwards pull from R16, and its presence has little effect. I will leave that resistor present in my own circuit below, for illustration purposes, but for now understand that when your upper switch is open, there's nothing except the ineffective R18 to lower gate potential. That's why your switches need to do that, pull down.

This is how one side of the bridge should look:

simulate this circuit – Schematic created using CircuitLab

Switches SW1 and SW2 operate in anti-phase, while one is on the other is off, and vice versa. They both pull gate potential low to 0V. Therefore R4 should be a pull-up, to 12V.

Start by understanding the state of the circuit when SW1 is on, and SW2 is off. M1's gate is at 0V now, which is necessary to switch that transistor fully off, regardless of the state of charge of C1. Conversely, with SW2 open, M1 is fully on, since its gate is pulled high by R4.

To answer to your first question, regarding the capacitors "ground", in this state, there is a low impedance path from +12V, through D1, C1 and M2 right down to ground. That causes C1 to charge up to 12V (actually slightly less since D1 has a small voltage across it).

When the switches change state, M2 turns off because its gate is now at 0V. Gate potential of M1 is pulled up via R1 and D1 to almost +12V (the diode drops a bit), which raises M1's source (remember it's working as a source follower) to few volts below that, say +8V. However, during the rise of potential at OUT to +8V, the bottom of C1 goes up with it. The top of C1 is almost 12V above that. During this rise, D1 becomes reversed biased and leaves the picture, leaving only R1 to apply this rising potential (well over 12V now) to M1's gate. It's a kind of positive feedback.

With its gate at well over +12V, M1 actually switches completely and utterly on, and OUT rises all the way to 12V, dragging its own gate way way up to nearly twice the power supply potential!

Here's a graph of the potentials at the gates over a few cycles:

Now to answer your second question, about calculation of the value of C1, you must understand how it discharges. You already get that it charges, gets "topped up" every time OUT goes low, but in the state where OUT is high, the current route for discharge is different. D1 is reverse biased, so that's not a route. The switch is open, so that's not a route.

The only route for the capacitor to discharge is via R1, R2 and R3 to ground. Their combined resistance, $$\R_1+R_2+R_3 \approx 11k\Omega\$$, combined with C1 produce a time constant of $$\\tau=11k\Omega \times 330nF = 3.6ms\$$.

You can see discharging happening above, the blue trace in the region between the green markers, where the voltage at M1's gate is decaying. The more frequently you switch states (ie. the higher the PWM frequency), the less time C1 has to discharge, so for higher frequencies C1 can be smaller.

This discharging can only happen for a few reasons, such as:

• Via R3, to ground
• The capacitor's own self-discharge
• leakage current through D1 or elsewhere

The biggest cause, by far, for capacitor discharge here, is R3. As I mentioned before, you don't even need R3, since the switch does all the pulling to ground. So I recommend you simulate that circuit without R3, to witness how the capacitor effectively never discharges:

In practice I would suggest a capacitance significantly greater than the MOSFET's own gate capacitance, say 100nF, but I welcome comments about this. Any current path to DC (ground or +12V for example) via which the capacitor can discharge, will determine the rate at which it discharges.

Here's the main point: you must never allow the capacitor to discharge so much that gate gets anywhere near the point at which the source starts to drop in potential, when the source starts to "follow". In other words, gate potential must always be significantly greater than $$\V_{SUPPLY}+V_{GS(TH)}\$$, where $$\V_{GS(TH)}\$$ is the MOSFET's gate threshold voltage, typically 3V or more.

From the first graph above, where gate potential decay is evident, since my MOSFET has $$\V_{GS(TH)}=4V\$$ the lower green marker must never get anywhere near +16V. That happens when I reduce C1 to cause faster discharge:

The orange curve is the potential at OUT. Notice how when the gate drops below +16V, the transistor's source begins to follow its gate, but 4V lower. This "linear" region is what you are trying to avoid with a bootstrap system. As you can see, it's simply not enough to apply +12V at the gate of M1, to turn it on. You need at least 16V at the gate, and that extra boost is provided by C1.

To your third question, "is my circuit good", I say no, it isn't. Make your switches pull down, and remove R18.

May I suggest you replace the physical switches with a MOSFET, to get this circuit:

simulate this circuit

M3 not only pulls down, but also inverts, so you only need the one signal to drive both M1 and M2.

As a final word, this is still not a good design, since there's nothing to implement dead-time to prevent shoot-through.

• Would you recommend a hardware solution or software solution to implement dead-time to prevent shoot-through? This might be an application specific question. Commented May 25 at 0:18
• @JasonC if you have control of the two FETs in software, with independent signals, then software can do it. If there's only one signal, then hardware will be necessary to delay the edge on the FET being activated. Commented May 25 at 8:52