We are using an ATSAMD51P19A and the Timer/Counter for Control Applications (TCC) to detect the pulse width from the assertion of a pin to the detection of a signal on another pin, and are having trouble achieving our desired resolution of +/- 10 nsec.

The below block diagram shows our Atmel START configuration to capture the pulse width.

enter image description here

Using a delay generator, we know the time delta from the assertion of the pin PA23 to the rising edge of the pin PA22 is 720 nsec +/- 5 nsec. Given our configuration, we expected that we could capture a pulse width of 720 nsec +/- 10 nsec. However, we are seeing 720 nsec +/- 50 nsec. Our application requires +/- 10 nsec, so the +/- 50 nsec is undesirable.

We have tried many configurations and have been unable to achieve an accuracy better than +/- 50 nsec. Any suggestions or feedback on how to achieve a higher resolution would be greatly appreciated.

  • 1
    \$\begingroup\$ What clock speed are you running at? \$\endgroup\$
    – Andy aka
    Mar 18 at 15:26
  • \$\begingroup\$ What does the doc say about input synchronisation delay with async inputs? I’d expect the input has to be valid for a couple of clocks. There may be other gotchas - read the doc carefully especially for async inputs. \$\endgroup\$
    – Kartman
    Mar 19 at 12:48
  • \$\begingroup\$ The CPU and TCC clocks are 120 MHz. We are required to configure the TCC to use ASYNC mode, as per the errata (DS80000748M): "TCC peripheral is not compatible with an EVSYS channel in SYNC or RESYNC mode." I agree it is possible there may be a gotcha with running in ASYNC mode, but as best we can tell, the datasheet doesn't expand further on what those could be. We would like to run in SYNC or RESYNC mode, but that's not an option per the errata. \$\endgroup\$
    – amasmiller
    Mar 20 at 12:30

1 Answer 1


We resolved our own issue.

The root cause of our problem was an oscillation on the MCU_VDDCORE/MCC_VSW supply rails of the ATSAMD51P19A, which was caused by the the low capacitor value connected to the MCU_VDDCORE/MCU_VSW circuit.

By adding a larger capacitor to the MCU_VDDCORE/MCU_VSW circuit, we removed the oscillation, which in turn solved our timing issue. Our variance went from +/- 50 nsec to +/- 10 nsec.

  • \$\begingroup\$ amasmiller - Hi, Thanks for coming back with an answer (interesting!) to your question. (a) In order to effectively mark the topic as solved, please consider "áccepting" your choice of the best answer (i.e. click the "tick mark" next to an answer - either your answer or another one, if one is written - to turn its tick mark green). This shows that you don't need more help & future readers can quickly see the confirmed solution. (b) At the very end of your answer, do you mean "Our variance went from +/- 50 nsec to +/- 10 nsec."? Thanks. \$\endgroup\$
    – SamGibson
    Mar 22 at 23:12
  • \$\begingroup\$ Yes, corrected. Thanks! \$\endgroup\$
    – amasmiller
    Mar 23 at 19:13

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service and acknowledge that you have read and understand our privacy policy and code of conduct.

Not the answer you're looking for? Browse other questions tagged or ask your own question.