# Why do both of these logic gate designs for an OR gate from NANDs work?

I was fiddling around with logic gate designs because I'm self-educating myself about electronic circuits and as a programmer the logic gate aspect intrigued me. I came across the simple "task" of creating each type of basic logic gate (NOT, AND, OR) out of NAND gates.

The NOT and the AND didn't give me much trouble, but I struggled a bit with the OR gate. I had been doing the "schematics" using the website logic.ly so I could see the resulting output get "processed" through each gate from the inputs using simple switches. I finally (kind of by accident) found a working schematic for an OR gate, as shown below:

As you can see, the input -> output result is correct for an OR gate;
0, 0 = 0
1, 0 = 1
1, 1 = 1
0, 1 = 1

I was super excited and decided to "verify" my answer by looking up the answer. To my surprise, it was quite different from my found solution.
Instead of hooking up the lower NAND (lets call it NAND 2), with one input connected to NAND 1, and the second input connected to input 2, it had NAND 1 and NAND 2 connected to input 1 and input 2 respectively, both taking a single input across both input wires (apologies if that explanation was confusing, I'll include a picture below). This got me pretty confused, and left me with two questions.

1. Why do these two different "solutions" or layouts, result in the same logical "OR" behaviour?
Why is the second design considered the "correct" or default design?
• 1. because they have the same truth table ... 2. the second one requires only a 1 second viewing time to determine what it does, the first one takes longer, becwise its function is somewhat obfuscated ..... also, research logic circuits race condition Mar 19 at 2:15