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I was fiddling around with logic gate designs because I'm self-educating myself about electronic circuits and as a programmer the logic gate aspect intrigued me. I came across the simple "task" of creating each type of basic logic gate (NOT, AND, OR) out of NAND gates.

The NOT and the AND didn't give me much trouble, but I struggled a bit with the OR gate. I had been doing the "schematics" using the website logic.ly so I could see the resulting output get "processed" through each gate from the inputs using simple switches. I finally (kind of by accident) found a working schematic for an OR gate, as shown below:

enter image description here enter image description here enter image description here enter image description here

As you can see, the input -> output result is correct for an OR gate;
0, 0 = 0
1, 0 = 1
1, 1 = 1
0, 1 = 1

I was super excited and decided to "verify" my answer by looking up the answer. To my surprise, it was quite different from my found solution.
Instead of hooking up the lower NAND (lets call it NAND 2), with one input connected to NAND 1, and the second input connected to input 2, it had NAND 1 and NAND 2 connected to input 1 and input 2 respectively, both taking a single input across both input wires (apologies if that explanation was confusing, I'll include a picture below).

enter image description here

This got me pretty confused, and left me with two questions.

  1. Why do these two different "solutions" or layouts, result in the same logical "OR" behaviour?
  2. Is there any inherent advantage or disadvantage to either design?
    Why is the second design considered the "correct" or default design?
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    \$\begingroup\$ 1. because they have the same truth table ... 2. the second one requires only a 1 second viewing time to determine what it does, the first one takes longer, becwise its function is somewhat obfuscated ..... also, research logic circuits race condition \$\endgroup\$
    – jsotola
    Mar 19, 2023 at 2:15

1 Answer 1

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The last NAND can only turn off if both of its inputs are on. That's the important scenario.

See that in your circuit, the last gate's bottom input is turned ON when both switches are on. In the other circuit, it's OFF. But it makes no difference, because in this scenario the last NAND is already on because its top input is off. Changing the bottom input makes no difference if the top input stays off.

The second circuit is more simple, so it's better. In reality you can make a NOT gate using the same design as a NAND or NOR but with only one input, and the second circuit would be made with two NOT gates and a NAND. Your one is more complex.

Because it's more complex, your one also has a longer path through it. If the gates don't operate instantly, then to make sure the output updates after the input changes, you would have to wait for three gate-delay-times. The second circuit needs only two.

Your circuit is susceptible to "glitching", which does not mean it works incorrectly, but means the output may become incorrect for a moment after the input changes, even though the output should stay the same. When both switches are on, the output is on. When then the top one turns off, if the gates don't operate instantly, the second gate updates before the third gate and for a moment the output turns off and then turns back on. This can be dealt with, but it makes your gate unsuitable for some purposes. The second circuit does not have this problem.

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