I have some Verilog code for which I am unsure of the outcome of the non-blocking assignment of x as shown below :
always @(posedge clk, negedge rst) if (~rst) x <= 1'b0; else begin x <= a; // Some value by default. if (~y) begin ack <= 1'b1; if (z) x <= ~x; end end
Assuming a reset is done at some point before the always block execution, then once the reset is cleared the always block should execute the rest of the code. The initial value of x would be 0.
So I assume this is set to schedule x <= a, then if y==0, ack is set to 1, and then if z==1 the x value is toggled.
Now if I've correctly understood how the scheduling is done for the non-blocking assignments, the right-hand side of the statements are all calculated first simultaneously, and then are all assigned simultaneously to the left-hand side of the corresponding statements, just before the start of the next positive edge of the clock-cycle (or possibly at the posedge of the next clock cycle).
This leaves me wondering what happens to x since it's scheduled to be assigned with a, and also assigned to be toggled if the condition is satisfied.
My question is what is the value that will be assigned to x in this case, is it a or ~x ?