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I have some Verilog code for which I am unsure of the outcome of the non-blocking assignment of x as shown below :

always @(posedge clk, negedge rst)
    if (~rst)
        x <= 1'b0;
    else
    begin
        x <= a;             // Some value by default.

        if (~y)
        begin
            ack <= 1'b1;
            if (z)
                x <= ~x;
        end
    end

Assuming a reset is done at some point before the always block execution, then once the reset is cleared the always block should execute the rest of the code. The initial value of x would be 0.

So I assume this is set to schedule x <= a, then if y==0, ack is set to 1, and then if z==1 the x value is toggled.

Now if I've correctly understood how the scheduling is done for the non-blocking assignments, the right-hand side of the statements are all calculated first simultaneously, and then are all assigned simultaneously to the left-hand side of the corresponding statements, just before the start of the next positive edge of the clock-cycle (or possibly at the posedge of the next clock cycle).

This leaves me wondering what happens to x since it's scheduled to be assigned with a, and also assigned to be toggled if the condition is satisfied.

My question is what is the value that will be assigned to x in this case, is it a or ~x ?

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1 Answer 1

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When there are two non-blocking assignments to the same variable scheduled in the same event region, and the order of those assignments is determinate, the last write wins. See section 4.6 Determinism in the IEEE 1800-2017 SystemVerilog LRM

In your example, the last conditional assignment to x uses the current value of x, not the unconditional default value that has been scheduled, but has not occurred yet. So it will toggle of all the conditions are met.

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  • \$\begingroup\$ Hi, thanks for the answer, that's interesting ... So this would apply to any other conditional assignments, say further down given they are determinate etc ... I was wondering what this "order of precedence" of non-blocking assignments is termed in Verispeak (if there is a term for it) as it seems to have eluded my quick searches in various books I was looking at to find the answer ?? \$\endgroup\$
    – davos
    Commented Mar 19, 2023 at 15:57
  • \$\begingroup\$ @davos See the reference to Determinism I just added to my answer Then see stackoverflow.com/help/someone-answers \$\endgroup\$
    – dave_59
    Commented Mar 19, 2023 at 19:34
  • \$\begingroup\$ This also works the same way for synthesis. However, for synthesis, the logic block is elaborated completely at compile time and modeled using flip flops and combinatorial logic. The realized hardware no longer contains multiple assignments. It is perfectly valid to code this way. You can think of the first assignment as the default value if there is no subsequent assignment that applies. In this case, the inputs are a,x,y,z, and the output is x. When synthesized, a block of logic will be created that defines x for all 16 possible input states. \$\endgroup\$
    – Troutdog
    Commented Apr 24, 2023 at 19:11

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