Yes, it is special.
Some classic reading may be of interest:
A Seven-Nanosecond Comparator for Single Supply Operation, Jim Williams | Linear Technology (Analog Devices)
As an overview, such a device has gain and phase shift such that it's stable in a feedback loop, like an op-amp. We might still need a more restricted sense of "stability" here: it might not be unity-gain stable (can have OUT strapped to -IN: phase is <180° at gain = 1) like most op-amps, but we might still be able to apply some (lesser) negative feedback to it (e.g., a divider from OUT to -IN to GND), without it oscillating. The resulting stable gain might be 100s or 1000s, maybe not very useful as an op-amp, but stable nonetheless.
And, mind that the comparator's output structure might not be designed for continuous linear operation anyway, i.e. supply current draw might be anomalously high while the output is at intermediate voltages. This might be the case for a CMOS output structure for example (a series of CMOS inverters, drawing full shoot-through current at intermediate voltages).
Incidental amounts of feedback occur, in use, due to finite supply and source (signal) impedance, capacitance between (and inductance of) pins, etc. So it's a helpful property. That, or hysteresis.
Hysteresis type comparators deal with this by making the input threshold (hopefully) larger than the expected feedback ratio, so that none of these effects (at these typical levels) are quite enough to cross the threshold. That is, say the output transition is whatever, a 5V step say, and some small fraction of it, maybe 1/1000th or 5mV, couples back into the input(s), in either polarity, and including rebound (it could be ±5mV depending on which input pin is predominantly coupled to, or if ringing is present). If the hysteresis band is more than 5mV, it won't chatter/oscillate: success!
Note that, if we include the possibility of positive feedback in our classification, then DC gain necessarily must be limited, otherwise positive feedback (at any frequency down to DC*) causes oscillation or hysteresis. It appears this may be relevant for the MAX913's case.
*Positive feedback at DC itself causes hysteresis, which we might not be too concerned about. It does still constitute instability, because the system might then be in one of two states, rather than one unique, stable state.
Unstable comparators, then, have excessive gain and phase shift, when accounting for some minimal amount of feedback. This arises where comparators and op-amps diverge: whereas an op-amp can only have so many amplifier stages before excessive phase shift occurs, comparators are not (necessarily) concerned about the same, and can simply stack up more stages to win higher
So there are kind of two approaches to comparator design. One, start with a stock op-amp, rip out the compensation capacitor, and maybe simplify the output stage. For example, compare LM324 to LM339. The latter is very similar to the former, but discards the output biasing and current limiting circuitry (it's an open-collector type output instead), and is decompensated so switches in ~300ns rather than ~10µs. Both have similar supply current consumption and supply and input voltage ranges, and are made on the same process (i.e. classic 1970s single-metal bipolar, using the hack of lateral PNPs for input diff pair and biasing).
Alternately, you can start with an op-amp's input stage (to get the wide range differential response), and just stack a ton of amplifier stages after it to boost gain at the expense of propagation delay. Gain is required, because each amplifier stage is working against its own capacitance, and so has a limited rise/fall (transition) time at its output. Some modest amount of drive current is required by the final (output / pin driver) stage, because it's made with bigger transistors (more capacitance).
Using few stages will get a low phase shift through the circuit, but this doesn't translate to low propagation delay because much time is spent in transition (output rise/fall time is slow).
But using many stages will get a large phase shift through the chain; that is, each stage's propagation delay adds up. At some point, the sum of delays dominates, and you might have a very crisp output (fast risetime), but it's delayed much longer than needed relative to the input.
A minima exists between these extremes, where enough stages are used to reduce output risetime, but not so many that overall propagation delay is increased.
The downside to this architecture is, each stage contributes its own phase shift, leading to real delay overall; that is, phase shift increases proportionally with frequency. When enough phase shift (180° and beyond) occurs, while loop gain (total gain times feedback) is above 1, oscillation occurs. If many stages are used so that the gain is very high, it doesn't take much feedback to cause oscillation, and indeed perhaps such a comparator is never stable in circuit (near transition).
This approach is typical of CMOS circuits, where gain is cheap: just tack on more CMOS inverter stages (merely two transistors each). It's especially typical in digital logic families, where -- remember digital signals are always analog on-board (voltage and current are continuous with time), so we can understand logic input pins as comparators converting external analog signals to internal digital states (a one-bit ADC), and output pins as the inverse (one-bit DACs). Buffered logic families are especially common (CD4xxxBE, 74HCxx, etc.), meaning that even a basic inverter (74HC04, etc.) has at least three stages internally. This has implications for the stability (and potential misuse) of these devices -- one gate can have enough delay that it oscillates on its own (ring oscillator), making it difficult or even impossible to construct certain blocks, like flip-flops (a positive feedback loop) or oscillators. (This is why certain devices are provided, like the unbuffered 74HCU04 inverter for oscillator and other applications. It's literally just the bare output stage; well, with ESD protection still attached.)
To clarify, I'm not aware of any standards that may exist regarding methods of measuring comparator stability. Possibly there are internal/proprietary or industry-wide standards controlling this; semiconductor standards are surprisingly opaque, so my not having seen any is hardly an indication of their absence. As always, go to the source: ask a manufacturer for more information.