These two comparators here MAX913 and MAX9013 are comparators that do not contain hysteresis. They are advertised to remain stable in the linear region and not exhibit instability for slow moving signals at the threshold.

I have two questions:

  1. Wouldn't other comparators that do not have built-in hysteresis also behave in the same way? Is this behaviour actually special? Does the the output not transition smoothly for a comparator with no hysteresis? Now that I think about it, I guess this is one of the differences between an opamp and a comparator and the comparator has some kind of circuitry to quickly drive the output between logic states that tends to result in instability in this region?
  2. What kind of applications would you use this comparator for? It seems to me that even though the output might transition smoothly, this output is always fed into a digital input which does have a region of indeterminant logic so what good is it?
  • \$\begingroup\$ I'm not sure what you mean here --> Wouldn't comparators that do not have built-in hysteresis behave in the same way <-- the same way as what? \$\endgroup\$
    – Andy aka
    Mar 19 at 22:25
  • \$\begingroup\$ @Andyaka In the same way as the aforementioned comparators. \$\endgroup\$
    – DKNguyen
    Mar 19 at 22:30

2 Answers 2


This behavior is quite special. As shown in the MAX913 datasheet on page 5 (bottom right, response to slow-moving triangle wave), a lot of comparators without hysteresis start to oscillate as they approach their linear region. The reason for that is that the gain of the comparator is so high (to ensure saturated digital output signals) that even the tiniest coupling from the output to one of the inputs (or an internal node) introduces enough feedback into the system that it starts to oscillate. Comparators usually don't employ any form of frequency compensation as they aren't meant to be used in a closed-loop system, and due to their high gain, even the tiniest bit of parasitic feedback is enough for oscillation to start. This kind of coupling can (and will) even happen internally to the chip; for example, the comparator's power draw will change as its output transitions from one state to the other, thereby introducing small voltage drops along the bond wires or even along the metallization layers of the silicon chip itself. If care isn't taken to ensure that these tiny disturbances can't influence the comparator's input stage, oscillation ensues. Most comparators therefore employ a very small hysteresis that biases the input stage away from the ultra-high-gain linear region in all cases, bringing the loop gain below unity even in the presence of parasitic coupling from the output to the input (which you can never avoid).

A slow-moving signal is any signal that doesn't get into and back out of the comparator's linear region within the propagation delay of the comparator. For example, if your comparator has an output voltage of 0V/5V (CMOS levels) and a gain of 50k, its linear region is 100µV wide. Assuming that it has a propagation delay of 100ns (at low input overdrive), the input signal has to slew at a rate of at least 100µV in 100ns, which is 1 volts per millisecond. The example scope trace shown in the MAX913 datasheet shows what happens to a "normal" comparator at 0.5 volts per millisecond: It oscillates like crazy. These aren't just "mechanical" timescales (milliseconds), but electrical timescales (microseconds / nanoseconds) in which the linear region has to be crossed, which is why most fast comparators these days have a bit of hysteresis, typically on the order of 1mV - a bit more than the size of the linear region.

As far as I can tell, the MAX913 simply doesn't strive for maximum voltage gain as other comparators do, but instead only has a modest gain of typically 3500. This is also a perfectly valid way to bring the loop gain below unity in the presence of parasitic output-to-input coupling, so it allows the comparator to be stable even without hysteresis.

You'd usually employ a comparator like the MAX913 in a circuit where you need to detect the level of a slow-moving signal with extremely high precision. Hysteresis introduces a fair amount of uncertainty to the exact level of the input signal as the hysteresis of many comparators is only loosely specified. Let's assume you want to detect whether a signal is above or below a certain set threshold with 1mV accuracy. If your comparator has 5mV hysteresis, you can simply forget about ever reaching that accuracy goal. However, you can't just use any old comparator that doesn't have hysteresis if your signal moves slowly, or else you're going to get oscillations, as previously described. You need a comparator that is specifically designed to not become unstable when it operates at or near its linear region, and the comparators you listed are ideal candidates for that.

The extremely low offset voltage drift of just 2µV/°C of the MAX913 is another dead giveaway that this comparator is designed to detect tiny variations in an input voltage that constantly hovers around the detection threshold with great precision.

When you employ the MAX913 in a circuit where you need an extremely accurate detection threshold (and consequently, where the MAX913 will spend a lot of time operating near its linear region), you would usually cascade two comparators: The MAX913 first to get an accurate, but potentially slowly-transitioning logic output signal, followed by a second comparator that has a bit of hysteresis to turn the MAX913's output into a logic signal with fast edges. That way, you get the accuracy and freedom of oscillations of the MAX913, as well as the fast edges from the secondary comparator.

In such a cascaded circuit, the hysteresis of the secondary comparator is effectively attenuated by the gain of the MAX913 (which is at least 1500), which means that you can reach single-digit microvolt precision even if your secondary comparator has a hysteresis of a few millivolts.

  • \$\begingroup\$ Could you give a better feel to what "slow moving" feels like? Are we talking electrical or mechanical time scales? I was looking at these and thinking about BEMF detection for sensorless motor commutation, particularly on startup. Or for current sensing for synchronous rectification which benefits from more precision at low levels. \$\endgroup\$
    – DKNguyen
    Mar 19 at 21:01
  • \$\begingroup\$ Given the low signal amplitudes involved in synchronous rectification current sensing, the slew rate is likely going to be too low to prevent a "hysteresis-less" ultrafast (10ns) comparator from oscillating. If you amplify the signal before feeding it into the comparator, it might be a different story, but then you could also just use a comparator with hysteresis. \$\endgroup\$ Mar 19 at 21:05
  • \$\begingroup\$ I see. Well I would have been using a current diff amp in any case, and not feeding the comparator directly. \$\endgroup\$
    – DKNguyen
    Mar 19 at 21:27
  • \$\begingroup\$ If you have a diff amp anyway, simply increasing the gain of the amp has the same effect as inserting a MAX913 (if you ignore its latch function). Both amplify the signal further before it's fed into the "final" comparator, thereby attenuating the effect of the hysteresis on the actual detection threshold. It doesn't have to be a MAX913, any other differential amplifier with low enough offset voltage will do in that case. \$\endgroup\$ Mar 19 at 21:33
  • \$\begingroup\$ Is "0V/5V" a typo? \$\endgroup\$
    – JRE
    Mar 20 at 5:56

Yes, it is special.

Some classic reading may be of interest:
A Seven-Nanosecond Comparator for Single Supply Operation, Jim Williams | Linear Technology (Analog Devices)

As an overview, such a device has gain and phase shift such that it's stable in a feedback loop, like an op-amp. We might still need a more restricted sense of "stability" here: it might not be unity-gain stable (can have OUT strapped to -IN: phase is <180° at gain = 1) like most op-amps, but we might still be able to apply some (lesser) negative feedback to it (e.g., a divider from OUT to -IN to GND), without it oscillating. The resulting stable gain might be 100s or 1000s, maybe not very useful as an op-amp, but stable nonetheless.

And, mind that the comparator's output structure might not be designed for continuous linear operation anyway, i.e. supply current draw might be anomalously high while the output is at intermediate voltages. This might be the case for a CMOS output structure for example (a series of CMOS inverters, drawing full shoot-through current at intermediate voltages).

Incidental amounts of feedback occur, in use, due to finite supply and source (signal) impedance, capacitance between (and inductance of) pins, etc. So it's a helpful property. That, or hysteresis.

Hysteresis type comparators deal with this by making the input threshold (hopefully) larger than the expected feedback ratio, so that none of these effects (at these typical levels) are quite enough to cross the threshold. That is, say the output transition is whatever, a 5V step say, and some small fraction of it, maybe 1/1000th or 5mV, couples back into the input(s), in either polarity, and including rebound (it could be ±5mV depending on which input pin is predominantly coupled to, or if ringing is present). If the hysteresis band is more than 5mV, it won't chatter/oscillate: success!

Note that, if we include the possibility of positive feedback in our classification, then DC gain necessarily must be limited, otherwise positive feedback (at any frequency down to DC*) causes oscillation or hysteresis. It appears this may be relevant for the MAX913's case.

*Positive feedback at DC itself causes hysteresis, which we might not be too concerned about. It does still constitute instability, because the system might then be in one of two states, rather than one unique, stable state.

Unstable comparators, then, have excessive gain and phase shift, when accounting for some minimal amount of feedback. This arises where comparators and op-amps diverge: whereas an op-amp can only have so many amplifier stages before excessive phase shift occurs, comparators are not (necessarily) concerned about the same, and can simply stack up more stages to win higher

So there are kind of two approaches to comparator design. One, start with a stock op-amp, rip out the compensation capacitor, and maybe simplify the output stage. For example, compare LM324 to LM339. The latter is very similar to the former, but discards the output biasing and current limiting circuitry (it's an open-collector type output instead), and is decompensated so switches in ~300ns rather than ~10µs. Both have similar supply current consumption and supply and input voltage ranges, and are made on the same process (i.e. classic 1970s single-metal bipolar, using the hack of lateral PNPs for input diff pair and biasing).

Alternately, you can start with an op-amp's input stage (to get the wide range differential response), and just stack a ton of amplifier stages after it to boost gain at the expense of propagation delay. Gain is required, because each amplifier stage is working against its own capacitance, and so has a limited rise/fall (transition) time at its output. Some modest amount of drive current is required by the final (output / pin driver) stage, because it's made with bigger transistors (more capacitance).

Using few stages will get a low phase shift through the circuit, but this doesn't translate to low propagation delay because much time is spent in transition (output rise/fall time is slow).

But using many stages will get a large phase shift through the chain; that is, each stage's propagation delay adds up. At some point, the sum of delays dominates, and you might have a very crisp output (fast risetime), but it's delayed much longer than needed relative to the input.

A minima exists between these extremes, where enough stages are used to reduce output risetime, but not so many that overall propagation delay is increased.

The downside to this architecture is, each stage contributes its own phase shift, leading to real delay overall; that is, phase shift increases proportionally with frequency. When enough phase shift (180° and beyond) occurs, while loop gain (total gain times feedback) is above 1, oscillation occurs. If many stages are used so that the gain is very high, it doesn't take much feedback to cause oscillation, and indeed perhaps such a comparator is never stable in circuit (near transition).

This approach is typical of CMOS circuits, where gain is cheap: just tack on more CMOS inverter stages (merely two transistors each). It's especially typical in digital logic families, where -- remember digital signals are always analog on-board (voltage and current are continuous with time), so we can understand logic input pins as comparators converting external analog signals to internal digital states (a one-bit ADC), and output pins as the inverse (one-bit DACs). Buffered logic families are especially common (CD4xxxBE, 74HCxx, etc.), meaning that even a basic inverter (74HC04, etc.) has at least three stages internally. This has implications for the stability (and potential misuse) of these devices -- one gate can have enough delay that it oscillates on its own (ring oscillator), making it difficult or even impossible to construct certain blocks, like flip-flops (a positive feedback loop) or oscillators. (This is why certain devices are provided, like the unbuffered 74HCU04 inverter for oscillator and other applications. It's literally just the bare output stage; well, with ESD protection still attached.)

To clarify, I'm not aware of any standards that may exist regarding methods of measuring comparator stability. Possibly there are internal/proprietary or industry-wide standards controlling this; semiconductor standards are surprisingly opaque, so my not having seen any is hardly an indication of their absence. As always, go to the source: ask a manufacturer for more information.


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