# Simulating AC-Coupling capacitor used in PCIexpress

I am trying to simulate and understand the AC-Coupling capacitor effect on signals with DC bias. I have a signal which has excursions between let's say 0.5V to 1.5V, So, it has 1V(0.5+1.5/2) DC bias. I thought 1V DC bias will be removed from the AC coupled signal and output(Signal after capacitor) will have excursions in between -0.5V to 0.5V. I may be wrong.please correct if i am wrong.....

But simulation gives waveform having excursions between 0 to 1V. I don't know How to explain this theoritically. I have used LTspiceIV from Linear technology and also Micro-Cap. Both given same result.

If you look carefully at the graph, you will see that the average voltage after the coupling capacitor is slowly drifting down -- at first the bottom is 0.0V and the top is 1.0V, but after the 4th pulse the bottom is almost -0.1V and the top is almost 0.9V.

I expect that if you run a longer simulation with 100 pulses, the average level will become 0V as you were expecting.

You can calculate the time constant based on your component values as $$\tau = RC = (100\:\Omega)(1\times10^{-10} \text{ F}) = 10\text{ ns}$$

It will take a few times longer, or about 30 ns, to settle.

Thanks for answering. Now i got it.

i am simulating with different values of C and rise and time periods of signals to see the effect of AC coupling capacitor. I will post my comments once i finished.

Thanks once again.

• Can you share your finding using different values of AC coupling caps on PCIe lanes. I am trying to understand what happens if I use 0.01uF or 0.1uF or 0.22 uF?? – Oshi Nov 9 '15 at 6:02