How does one set the Q-point for a JFET cascode amplifier, and what are the correct "Idss" requirements for cascoded JFETs?

I am trying to teach myself electronics, and am currently attempting to learn about cascodes with the intent of building an RF amplifier that will amplify a microvolt signal up to line level with minimal noise. My intended approach is a cascode (or cascodes) into an operational amplifier.

I think I understand setting the Q-point for a common-source amplifier and common-gate amplifier separately; for instance, if I wanted to set the Q-point for a CS using a 2N4416, I think I would construct a circuit like the one below (neglecting the DC blocking capacitors), which correctly simulates my intended values of VGS = -0.9 V, VD = 4.5 V, and IDS = 5 mA.

simulate this circuit – Schematic created using CircuitLab

However, I do not understand how I would extend this to a cascode, such as is illustrated by the schematic below (left being externally biased, right being biased by source of J2):

simulate this circuit

Between a myriad of textbooks, application notes, and blog posts spanning the past ~30 years, I have encountered a number of contradicting statements, especially concerning the use of identical J1 and J2, which have only left me more confused. My questions are:

1. Is identifying the drain and source resistance, RD and RS, for the cascode the same as for the common source amplifier? Do the Q-points of each transistor need to be set independently or are J1 and J2 a singular unit? None of the sources I've found has been clear on this.

2. The most confusing thing to me is the contradiction among numerous sources (e.g. the seemingly ubiquitous TangentSoft article on biasing Class A amplifiers, Erno Borbely's articles, TI application notes, a textbook excerpt (the book from which I am unable to deduce), and a couple of NIST papers on low-noise amplifiers) all disagree on whether or not J1 and J2 can be identical, with determinations ranging from it being totally OK, it being OK in some instances if you can buy 1000 JFETs and bin them by IDSS, and it being absolutely not OK because J1 must have a higher IDSS than J2.

What is the right answer? I am leaning towards accepting that the FETs can be identical since TI and Linear offer monolithic dual N-channel JFET packages (that look very appealing) and they surely wouldn't fabricate an IC that is predestined to fail. Does this mean that the requirement that J1 IDSS > J2 IDSS is not necessarily true, or is this conditional on the use of RS to limit the current across J1? How would RD play into this?

I hope these questions aren't foolish - I am happy to clarify any questions. As another note, I have been attempting to simulate the schematics in LTspice, but JFETs seem unreliable to simulate and the wide IDSS spread between models makes me nervous about the accuracy of the simulations.

My Current Understanding

To illustrate my current understanding as to how I would construct the cascode amplifier, consider the circuit below.

simulate this circuit

Using the information from the 2N3819 datasheet I assume a desired ID = IDSS/2 for maximum voltage swing, assuming a binned part with IDSS = 7 mA. Assumed values from datasheet are VGSoff = -2.2 V and desired VGS = -1.0 V and VD = 18 V. Power supply is a 24 V battery.

From these charts, I want ID = 3.5 mA, so I can determine RD from VD = VDD-(ID RD), yielding an RD of ~1.7 kOhms (1.69k to nearest value in LTSpice part database).

The source resistance is then determined from RS = |VGS/ID| = ~286 Ohms (287 via LTSpice).

This nets a VGS in both JFETs of approximately -1.2 V.

VDS for each JFET is J1 = ~10 V and J2 = ~5 V, which puts both transistors squarely in their saturated region.

DC blocking capacitors were chosen as a high pass filter >100 Hz, and the bypass capacitor CS chosen for the 38 kHz (1 mV amplitude) frequency used in this example.

Given all of the above information, have I approached this correctly? Would this yield a feasible cascode amplifier circuit?

Beyond formal classifications

Formalisms simplify and facilitate our work, but they make us not think and apply ready-made patterns. Such is the formal "common-something stage" classification of transistor amplifier stages, or more specifically in this case, the representation of the cascode circuit as cascaded "common-source" and "common-gate" stages.

Intuitive (true) understanding of electrical circuits requires that we descend to an even lower functional level where we can explain circuit phenomena with equivalent "man-controlled" electrical circuits. By performing (slowly and even step by step) the functions of active devices, we understand what they do. I have demonstrated this heuristic approach with the fancy story below dedicated to this brilliant circuit solution.

Basic idea

If we connect two heterogeneous electrical sources (voltage and current) to each other, they will keep their quantities ​​constant and provide each other with ideal load conditions: the voltage source will "see" an open circuit and the current source - a short circuit. As we will see below, they even "help" each other when one of them (the current source here) tries to change its quantity.

So the cascode circuit can be thought of as a current source driving a voltage source.

Building a cascode circuit

Let's see how this basic idea is implemented in the cascode circuit by building it step by step.

STEP 1: Current source drives voltage source

For example, in the figure below, a current source passes 2 mA through a voltage source and the voltage source maintains 5 V across the current source.

simulate this circuit – Schematic created using CircuitLab

STEP 2: Rearranged circuit diagram

Let's draw the sources so that the circuit diagram matches the next steps. Also add the measuring instruments (ammeter and voltmeter) needed for the following experiments.

simulate this circuit

STEP 3: Resistor implementation

In electrical circuits, we use only one voltage source (power supply) to produce many voltage drops and currents across/through resistors. We call them "voltage sources" and "current sources" although they do not produce but consume power.

In electronic circuits, current and voltage sources are implemented by transistors. For purposes of intuitive understanding, they can be thought of as "resistors" with "static" resistance Rce = Vce/Ic that are controlled by the base-emitter (gate-source) voltage.

So, it is extremely useful for the purpose of intuitive understanding to replace transistors with variable resistors controlled by us. Playing the role of the transistor we will understand exactly what it does in this circuit.

simulate this circuit

As you can see from the schematic above, RI plays the role of J2, and RV plays the role of J1 from the OP's circuit. Specifically, RI sets the current (by the help of RV), and RV sets the voltage (by the help of RI). In fact, the two resistors form a voltage divider in which the current is set by RV + RI and the voltage is set by RI/(RV + RI).

STEP 4: CircuitLab experiment

The "game". To imitate the behaviour of transistors in this virtuoso experiment:) requires a little more dexterity. The main problem is that the voltage and current are interdependent and require iterative adjustment. For example, suppose you want to increase the input current. You can do it like this: First, open the RI parameters window and begin slightly decreasing the RI resistance looking at the ammeter until it shows the desired current magnitude. Then look at the voltmeter... Ah, the voltage has slightly decreased:-( To increase (restore) it, close the RI window, open the RV parameters window and begin to gradually decrease the RV resistance looking at the voltmeter. Ah, but now the current has slightly increased:-( So repeat the procedure from the beginning... and so on until the voltage becomes 5 V again and the current has the desired value...

Interacting sources. Let's now see how the sources "help" each other. Let you be the voltage source and let me be the current source. When I want to increase the current, I start decreasing RI; but you see that the voltage Vref is decreasing and to increase it you also start decreasing RV. Thus you help me in my desire to reduce the total resistance and increase the current. So, we can conclude:

When the current source decides to set a new current magnitude, it begins changing RI to set a new total resistance RI + RV. As a response, the voltage source begins changing RV to keep the ratio RI/(RI + RV). Eventually they reach equilibrium (there is convergence in this procedure).

A game trick. It is quite slow... but this "game" can be played by two people... even remotely. By the way, you can use another simple trick. As you can see, I have selected identical starting resistances of 2.5k. You can directly change them at the same time; the voltage will not change because the ratio RI/(RV + RI) remains constant.

CircuitLab tricks. This "game" is a little difficult to play because CircuitLab is not designed for this purpose and we have to use some tricks such as:
- Measuring instruments. If the "parameters" window hides the measuring instruments, you can temporarily drag them away from the schematic so that you can see their readings. Or, you can temporarily connect new ones with long wires or wirelessly by labeled notes. See, for example, the schematic below.

simulate this circuit

- Labeled nodes. You can also temporarily drag away label nodes or connect wirelessly their copies with the original labeled notes to see them when the parameters window us open. By the help of the CircuitLab DC live simulation, hover the mouse over the labeled node and enter the parameter in the window while watching the reading.

simulate this circuit

- "Sliders". Yesterday I managed to find a way to imitate a "slider" in CircuitLab. The trick is this: For example, you want to vary resistance from 0 to 10k in 1 k steps. In the "parameters" field, you first write "0". Then you mark it and write "1" over it. So you continue with 2, 3... 10 k. As a result, you have the sequence memorized in the keyboard buffer and you can move backward (with CTRL X) or forward (with CTRL Y). Of course, this would be best done with the arrow keys (with "parameters" disappeared)... and that is a shout out to the CircuitLab designers:-)

STEP 5: Taking the output

Our "man-controlled cascode circuit" produces output current; but we need voltage. So, connect a resistor Rc acting as a current-to-voltage converter and take the complementary voltage Vout as a grounded output. It will disturb your circuit but you will compensate for it since you act according to the negative feedback principle.

simulate this circuit

As above, to see the voltages when the parameters window us open to the right, you can put to the left wirelessly connected copies of the labeled notes Vref and Vout:

simulate this circuit

STEP 6: BJT implementation

DC circuit. Now it remains only to replace the resistors with transistors and you get the real cascode circuit. I have started with BJT implementations because they are simpler. The procedure is similar to the above except here we adjust input voltages instead of resistances.

To set 2 mA current through Rc, I have increased ("lifted") Vin to 0.677 V in "Vin parameters" (this is the so-called "biasing"). Then, to set Vm = 5 V, I had to set the Vref = 5.678 V.

simulate this circuit

It is interesting to compare this transistor circuit with the "resistor one" above (STEP 5). As you can see, they are electrically equivalent - if you replace the transistors in STEP 6 with the resistors in STEP 5, or the resistors in STEP 5 with the transistors in STEP 6, nothing will change. So the corresponding "static" resistances are equivalent - RV = VRV/Ic = VQVce/Ic = RQIce and RI = = VRI/Ic = VQIce/Ic = RQIce.

AC circuit. Let's finally make an (almost) true AC cascode amplifier - for simplicity, without coupling capacitors and bias circuits. For this purpose, I have replaced the DC input voltage source with an AC one; then set a 10 mV AC input voltage and 0.677 V offset voltage in "Vin parameters" to "lift" the input AC voltage (bias QI).

simulate this circuit

Compared to the output voltage, the amplitude of the AC input voltage is too small (only 10 mV) to be seen on the graph, and the cascode circuit amplifies more than 100 times. We also see that the QI collector voltage (Vref) is constant (5 V) which is the purpose of this weird circuit configuration.

STEP 7: JFET implementations

Let's now consider the JFET implementations of this exotic circuit idea to directly help OP in solving their problem.

JFET is a weird device which, contrary to our intuition, is fully on when the input gate-source voltage is zero. In addition, an N-channel JFET requires a negative input voltage to be applied to the gate. This is quite annoying for us because we prefer to use only one power supply, preferably positive.

STEP 7.1: DC circuit (fixed biased). So, to bias an N-channel JFET, we need another but negative voltage source Vin. According to the procedure above, to set 2 mA current through Rd, I have applied -830 mV to J2 gate. Then, to set Vm = 5 V, I had to set Vref = 4.174 V.

simulate this circuit

STEP 7.2: DC circuit (self-biased). Fortunately, there is a solution that allows to avoid the second voltage source. If you insert a resistor Rs between the source and ground, the drain current begins flowing through it and a voltage drop appears across it. This voltage is positive regarding the ground but it appears negative to the gate-source input if the gate is connected through something (input source, resistor...) to ground. So, in the fixed biasing above, the gate is "lowered" below ground (being negative) while here the source is "lifted" (being positive)... but in both cases the gate-source voltage is negative. This negative voltage tries to turn off the transistor; but this decreases the current and voltage, and eventually equilibrium is reached. This mechanism is known as "negative feedback".

In this way, the transistor is "self-biased". You can adjust the bias voltage across Rs by changing the resistance. So, if there are a source resistor, you do not need to apply a negative voltage to the gate since it is already applied.

simulate this circuit

In the schematic above, I have adjusted Rs = 414 ohm. As a result, 828 mV appear across Rs and the current through Rd is 2 mA again.

STEP 7.3: AC circuit (fixed-biased). The difference with the above DC circuit (fixed biased) is that the DC source is replaced by a 100 mV AC source and -830 V offset voltage is added (in Vin parameters window) to "lower" the input AC voltage (bias QI).

simulate this circuit

STEP 7.4: AC circuit (self-biased). The only difference with the above DC circuit (self-biased) is that the DC voltage source is replaced by a 100 mV AC source. The offset voltage is 0 V since the biasing (Q-point) is provided by the voltage drop across Rs.

simulate this circuit

STEP 7.5: AC circuit (self-biased) with capacitors. Finally, let's make a practical AC cascode amplifier:
Voltage divider reference. In simulations, we can use many voltage sources but in real circuits this is impractical; so we get derivative voltages from the main power source. The simplest way to do this is with a voltage divider. To do it, we connect two resistors (R1 and R2) in series, supply this network and use the voltage drop Vref across R2 as a reference for the J1's gate.

simulate this circuit

Coupling capacitors. The usual explanation for so-called "coupling capacitors" is that "they stop DC and pass AC". Let's look at the problem from a different perspective and try to find a better explanation.
- Input capacitor. The AC input voltage applied to J2's gate should "wiggle" around ground. But it can be produced by the same amplifier stage; then it will "wiggle" around 8 V (I have imitated this situation by setting an 8 V offset in the Vin parameters window). So we have to somehow bring it down with 8 V (to the zero level)... i.e. to subtract 8 V from it. We can do it by connecting an 8 V voltage source with opposite polarity between the output of the previous stage and the input of this stage (J2's gate). In AC amplifiers, charged capacitors serve as such "shifting voltage sources". So, let's connect a capacitor C1 between the input voltage source and J2's gate. It will be charged through Rg and will act as an 8 V "rechargeable battery".
- Output capacitor. Similarly, the output of this stage ("lifted" to 8 V) can drive the input of another stage or any other load that "wiggle" around ground. So, we can apply the same technique connecting another coupling capacitor C2 between the output and the load RL (that is why, it should be "galvanic"). It will be charged through RL and will act as another 8 V "rechargeable battery".

Decoupling capacitors. The coupling capacitors above are "floating" and connected in series to AC voltage sources; so they transfer ("move", "shift") voltage variations. Conversely, if we connect a capacitor in parallel to a constant voltage source, it will make it "even more constant". Thus, the devices powered by it will not affect each other; they will be "decoupled".
- Reference decoupling capacitor. The imperfection of a simple "voltage divider source" as R1-R2 above manifests itself when a load draws current; so its output voltage drops. Fortunately, JFETs do not draw current but another problem can be the rapid supply variations. So, let's connect a "decoupling capacitor" Cref to the voltage divider's output. It will act as a kind of small "back-up battery" that keeps the voltage almost constant.
- Source decoupling capacitor. The resistor Rs inserted between the J2's source and ground introduces a negative feedback that is useful for DC but it decreases the AC gain. The problem is that the voltage drop across Rs varies following the input voltage variations and decreasing gate-source voltage. The remedy is obvious - shunting Rs by a decoupling capacitor Cs.

Finally, with the help of Time-domain simulation, let's see the voltages at the circuit points.

STEP 7.6: AC circuit (mixed-biased) with capacitors. It is possible to neutralize part of the source voltage by a constant voltage "produced" by another voltage divider. For this purpose, we only connect the J2's gate with another resistor R3 to Vdd.This gives more options for setting the J2 bias voltage.

simulate this circuit

• @normal chemist, JFET is a weird device which is fully on when the input GS voltage is zero. So, if you insert a resistor between the source and ground, the drain current begins flowing through it and a voltage drop appears across it. This (source) voltage is positive regarding the ground but is negative regarding the gate (that must be connected through something to ground), and it tries to turn off the transistor (negative feedback). Eventually equilibrium is reached. Thus the transistor is "self-biased". You can adjust this bias voltage by changing the resistance... Commented Mar 21, 2023 at 16:47
• ... or applying a positive voltage to the gate. The two voltages are subtracted and the result is applied to the GS junction. So, if there are a source resistor, you do not need to apply a negative voltage to the gate since it is already applied. You can apply a positive voltage to the gate that will neutralize a part of the negative source voltage. Maybe I should continue my answer with a JFET version of the cascode amplifier... Commented Mar 21, 2023 at 17:26
• This is my current attempt at making a sensible cascode (imgur.com/a/QwPR0CE) but the gain seems terrible, and I figure I must be missing some crucial piece of understanding. Commented Mar 21, 2023 at 17:35
• @Circuitfantasist "JFET is a weird device..." I bet it seemed a lot less weird than BJTs to people who had previously used self-biased triodes. Commented Mar 22, 2023 at 15:11
• @Circuitfantasist I have used your rationale and some of my current understanding to try to throw together what I think is a "complete" JFET cascode amplifier as an edit to my original question. If you have thoughts about it I would love to hear them. Commented Mar 22, 2023 at 18:12