# Open collector logic question

I have an instrument that I am trying to integrate some pumps with. It has 3 Open Drain pins,a ground, and a +5V pin.

I've successfully used 3 NPN transistors to act as a +5V switch to drive a relay when the Open Drain pins are high.

I have a problem when the instrument first turns on (or recovers from a power failure). It turns all 3 Open Drain pins high and turns on all 3 relays until it finishes initializing. I'd like to avoid this.

My idea is to use one of the Open Drain lines to act as a +5V supply when it is low (the initialized state) so that the other two lines will only be active when the instrument is fully initialized. How can I do that?

• A circuit diagram would be useful .. is it possible to invert the logical 'sense' of the open drain lines in the instrument? Or invert the logical sense of the relays (swap normally open for normally closed)? Apr 17, 2013 at 14:36
• Would all three relays ever need to be in a normal operation? Apr 17, 2013 at 14:38
• I meant would all three relays ever need to be on in a normal operation? Apr 17, 2013 at 14:46
• Open drain outputs are not "high" or "low". They either sink current to ground, or they don't. The translation to a high or low voltage level comes from an external resistance (which in some devices can be different from their supply voltage: lower, or even higher!)
– Kaz
Apr 17, 2013 at 16:59
• To suppress some unwanted startup behavior, you could always add some logic gates and a power-on pulse. Suppose that the relays activate not only when the open drain pins drive them, but also AND if some other logic level is high. This logic level doesn't go high until some RC circuit charges to a certain level, which is designed to take longer than the startup of that device.
– Kaz
Apr 17, 2013 at 17:01

If they are open-drain lines during initialization and they are pulling high then try a 1k pull-down resistor so that the 1k resistor wins the battle (after all it's probably only fighting against a weak pull-up during initialization). You need to check this.

After the unit has initialized it can drive the line (and transistors) and operate correctly.

Are you putting a resistor in series with the base on each transistor. Something like 1k should be fine.

• Let's see if I can describe the set up in text. I'm using an NPN transistor. The collector goes to ground. +5V goes through an 350 ohm resistor, then an LED, and then to the emitter. The open collector pin goes to the base, but there is a 10K resistor to the ground/collector and a 1K resistor to the +5V line. Clear as mud? :) Apr 18, 2013 at 14:55
• @LanceLarka mud is clearer so if ya can try and post a picture. Emitter should point towards 0V. Collector points towards +5V. LED between collector and +5V. Resistor either in series with emitter or LED are the options. Base via resistor (10k) to IO pin. Pull-down on IO pin. This is how i'd do it. Apr 18, 2013 at 18:59

You could use one of the two circuits below. The first circuit uses Q1-Q3 as an AND gates to control U2, which contains four SPST switches that turn on with logic 0. I am calling your 3 open drain pins CNTRL1, CNTRL2, and CNTRL3. If all 3 control lines at logic 1 (high), all 3 transistors are turn on, which causes all 3 switches to be turned off. I am not showing your pull up resistors for the 3 control lines. Please note that this circuit will only work for you if during normal operation, all the relays don't need to be turned at the same time. The second circuit replaces the transistors with a RC circuit and ADG201A with ADG202A which has switches that turn on with logic 1 ranter than logic 0.You can calculated values of R1 and C1 such that it is longer than the time required by your instrument to initialize.

• Many thanks. What software are you using to make these schematics? Apr 18, 2013 at 14:58
• I am using Orcad. Apr 18, 2013 at 16:59
• I think you mean for Q1-Q3 to be PNP devices? It won't work with NPN devices, as you drew it. Aug 16, 2013 at 1:51