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All my QFN footprints are made with the Altium internal "Tools -> IPC Compliant Footprint Wizard". I get nice footprints with vias in the thermal pad.

When I try to place one of those footprints to the PCB, I get an short circuit violation between the via and the pad. (Shown in the second Image).

How can I correct the rules to allow this vias? I have tried to make a rule (Image 3) that allows short circuit between pads and vias. But the problem here is that the vias are not connected to any net (no Net). If I want to connect them, I have to unlock the primitives and set each via to a net. This is a real ugly way of solving this problem :-(

enter image description here enter image description here enter image description here

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  • \$\begingroup\$ Shouldn't they be connected to a ground plane? \$\endgroup\$ – pjc50 Apr 17 '13 at 15:10
  • \$\begingroup\$ Yes, the Vias should be connected to the ground plane to give away the heat there. But they can not be assigned to GND during the footprint design (The name of the ground plane is not yet known in this stage) \$\endgroup\$ – Botnic Apr 17 '13 at 15:32
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This has been a bug in Altium for at least the last few versions. The footprint wizard does not apply pin numbers to the vias. I would recommend is you assign the vias the same pin number as the rectangular thermal pad in the footprint editor.
In my experience, this sometimes seems to work. Altium tends to get cranky when you have multiple pads/vias/whatever in the same footprint with the same number.


Anyways, You don't need to unlock the primitives to set the via's net. Press Ctrl+H to activate the Select connected copper mode. Then, just click anywhere in the thermal pad.
Then, in the PCB Inspector panel, you can simply edit the net for all the vias and the pad at the same time. If you set the net to whatever the ground pad is supposed to be, it will set the vias and the rectangular pad's net to the same.


Re: Allowing collisions between vias and the pad.
Globally allowing vias to intersect with component pads is very risky. I would change your rule to be:
Rule 1: InAnyComponent and IsVia
Rule 2: InNet('GND')

The reason your rule is not working is because your IsVia and InNet('GND') will only apply to vias that are already set to the net GND. Since your vias are set to NoNet, the rule is not being applied to the vias with which you are having problems.

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What "should happen" is when the component is placed, the pad will get a net, and the no-net vias should automatically take it's net.

The issue happens when you place the component on a plane/poly/fill that isn't the same net as the pad, and instead of taking the pads net, they take the plane/polys net and cause violation.

If you place the component before the plane/fill/poly it "should" work fine.

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Another way to address this issue is by using "Pads" in place of "Via" in library with the same designator of the thermal cooling tab/pad. You can add net to the tab/pad in pcb. enter image description here

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