If I'm not mistaken, single logic gates (i.e. a single NOT, OR, NOR, AND, NAND, XOR, etc.) do not exist (anymore?) in through-hole packages.

At least, on Digikey, when searching for active in-stock logic gates (all types) with through-hole mounting, there is a single reference in DIP-8 format, and all other are at least DIP-14 format.

Do you have any idea why there are no single gates? Did I look at the wrong place?

I know that through-hole is less and less used, but it is still very useful for fast prototyping on a breadboard or on prototyping PCBs (those with hole arrays, connect or not in lines).

I also suppose that producing a gate with several gates has about the same cost as a single gate (so it ends up cheaper due to economies of scale).

Most (95%?) of the time, only one (or sometimes 2) gates are required, so a DIP-14 package is a huge waste of PCB space (even on prototyping PCBs; one sometimes cares).

Why are there no single gates in DIP-4 package for NOT, DIP-6 package for other functions, or at least triple NOT and dual AND/OR/etc. in DIP-8 package in order to keep a common package?

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    \$\begingroup\$ Did they ever exist? If you make a little converter board (SMD to DIL) it will work for you yes? \$\endgroup\$
    – Andy aka
    Mar 22 at 11:37
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    \$\begingroup\$ Honestly, I don't know (I'm too young to have done electronics at the time when most components where still through hole). I suppose single gates existed at least in the early stages of "integrated circuits" (it's the logic step just after single transistors, and before mastering production of "complex" logic circuits). If they were manufactured ever since, no idea. \$\endgroup\$
    – Sandro
    Mar 22 at 11:43
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    \$\begingroup\$ @Sandro "it's the logic step", unfortunately sometimes (or often?) what is logic is not what drives industry. Market forces have a whole different "logic" than "engineering logic". After all, even if some among us EE may not like it (the more "sciency types"), industry does things to make money. That's also how usually engineers earn their pay :-) \$\endgroup\$ Mar 22 at 13:29
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    \$\begingroup\$ "I know that through-hole is less and less used, but it is still very useful for fast prototyping on a breadboard or on prototyping PCBs (those with hole arrays, connect or not in lines)." - smd to DIP adapters fill that role, eg. sparkfun.com/products/717 \$\endgroup\$ Mar 23 at 5:12
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    \$\begingroup\$ Any time you need only one logic gate you can easily implement it with one or two transistors, some diodes and some resistors for extremely low cost. The main reason for using ICs instead of implementing your own gates using transistors is when you need to use lots of gates in a single design thus the ICs will save you space and reduce component count. \$\endgroup\$
    – slebetman
    Mar 23 at 9:57

12 Answers 12


Historically, the 14 and 16 pin DIP package became the standard package for digital ICs. The reason is that you could get 4 AND/OR/NAND/NOR gates in a 14 pin package. More complex devices like 4-bit adders required 16 pins (8 inputs, 4 outputs, carry in, carry out, power, ground).

There was some early logic that was packaged in metal (TO-5?) cans (like transistors) with 6 or 8 leads, but that never found wide acceptance

I'm guessing that was the sweet spot from a cost/functionality standpoint in the late 60's/early 70's. A single inverter (NOT) would still require a 4-pin package, and the package, die mounting, wirebonding, etc may have cost more that the die. Also, a single inverter or AND gate may have been more difficult to slice & dice from the wafer in those days.

  • 1
    \$\begingroup\$ Exactly, there is also a crossover point where going fewer pins makes the cost go up, because they don't stand up properly, might have a backward aspect ratio, and are more fiddly for the machines to handle. \$\endgroup\$
    – doug65536
    Mar 24 at 5:51

First I'd say your premise that 95% of the time only one or two gates are needed is wrong. I'd also say that your other premise that a 14 pin dip package is a huge waste of PCB space is also questionable.

Generally when through hole ICs were popular you would be making one of two types of circuits, a large circuit requiring a lot of gates where the majority of gates in the standard packages would get used, or a circuit with only a couple of gates where you didn't really care about the size of the board, even with unused gates it still wouldn't be all that large. Back in those days it wasn't unusual to see boards with chips spread apart pretty far, unless you were building something to go to space size wasn't as much an concern as it is today. Take for instance this 1980's vintage board: commodore 64 board Obviously they weren't trying to pack things in very tight.

Photo from https://en.wikipedia.org/wiki/Commodore_64

  • 12
    \$\begingroup\$ It wasn't so much that size wasn't a concern -- it's that multi-layer boards weren't as common, and traces take space (even 2-layer plated-through boards were high tech in the late 70's, early 80's). Just look at the amount of board space taken up by traces in your example above. I'm guessing that it's a two-layer board, and that jamming more circuitry onto it would involve a lot of extra layout time. \$\endgroup\$
    – TimWescott
    Mar 22 at 23:21
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    \$\begingroup\$ @TimWescott: Also, these boards were laid out by hand (pencil, paper, stickers and tape) at that time. \$\endgroup\$ Mar 23 at 15:53
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    \$\begingroup\$ Actually, that one looks like it was laid out in a CAD program, at least to me. Hand-laid boards tend to have traces that look more organic. \$\endgroup\$
    – TimWescott
    Mar 23 at 22:16
  • \$\begingroup\$ I'm having a hard time remembering when we got our first schematic capture tools. I think is was 1990, Tek CAE, IIRC. I thought our drafting department, which did the actual layout and routing, had CAD tools before that. So it's very probably something from the mid 80's would have been laid out and routed with a CAD tool. \$\endgroup\$
    – SteveSh
    Mar 24 at 14:01
  • \$\begingroup\$ The company I worked for in 85/86 did CAD layout. We would use a large format plotter to plot them on clear film that was sent to the place that made the boards. And you could absolutely pack a double sided board much tighter than in the photo above if you really wanted to. \$\endgroup\$
    – GodJihyo
    Mar 24 at 14:33

tl; dr: single-gate SSI in DIP is inefficient space- and cost-wise, even in the earliest days of ICs. The economics of bigger packages like DIP favor(ed) more integration than just one function in the package.

DIP however is all but obsolete for product design, which is largely SMT now.

Meanwhile, single-gate 'tiny' logic in SMD has emerged as niche use in today's systems to fix system issues that are otherwise composed of larger ICs. This use case and its economics favor the smallest-possible package and very lowest cost, which are only achievable by SMT.

Here comes the history...

In the SSI (Small Scale Integration) era (c. 1965 ~ 1975), it was important to pack as many units into a package as possible. This was true regardless of whether the logic was in DIP or in smaller, more-exotic flatpack type packages favored by military and space systems.

The low amount of integration afforded by SSI at the time also meant that designs of that era were 'seas of gates', from which were constructed complex data paths and control blocks. SSI-era designs often contained dozens, hundreds, even thousands of packages.

It therefore made little sense to have SSI packages that had just one gate, one latch, one flop, etc., since most designs needed more than just one of anything. It would have just wasted space and increased cost to have single-function devices.

The very earliest mass-produced SSI IC, a dual NOR3 used in the Apollo Guidance Computer, came in a 10-pin flatpack. The AGC, which had the approximate compute power of the 6502, used about 4000 of those dual NOR3 ICs.

Even in those go-to-the-moon salad days of IC manufacturing, density mattered.

Speaking of manufacturing, commercial board designs up until the mid-late 1980s were largely through-hole; some even wire-wrap. Also, there was a desire to standardize ICs to specific shapes and formats for easier multi-sourcing and automated assembly. With this in mind, the industry got behind the 100 mil DIP format, and with the leadership of early movers like TI and Fairchild, the DTL, then later TTL families of parts was born and popularized in the easy-to-use DIP format.

As integration continued (c. 1970 ~ 1977), some common datapath constructs migrated from 'roll your own' blocks lashed-up from SSI functions into bigger MSI (medium-scale integration) chips. Standardized MSI datapath-oriented functional blocks came on to the market, such as ALUs, multiplexers, demultiplexers, buffers, byte-wide registers and so forth. SSI continued to be used in control (or 'glue') logic. Still, largely in DIP.

Later, the emergence of programmable logic devices (PLDs) (c. 1978) from MMI and Signetics further supplanted SSI gates in many designs. Boards of the PLD era usually had some MSI datapath elements; while 'glue’ logic consisted of fewer SSI gates as the 'glue' was done in PLDs instead. A classic, late-70's example of PLD-oriented design can be found in the Data General MV/8000, the subject of Soul of a New Machine. You guessed it, still in DIP.

Large Scale Integration (LSI) devices (c. 1975 ~ 1990), in turn, devoured MSI, and to an extent, SSI. A state-of-the-art mid-1980's era LSI-based microprocessor board would have the CPU, RAM, ROM, some peripheral LSIs, maybe a couple of octal buffers a couple of latches, and a PLD or three for glue logic. A cost-reduced design might use SSI instead of PLDs. But, still in DIP and other through-hole like pin-grid array, with SMT beginning to make inroads toward the end of the 80's.

Meanwhile, what was also happening in the late 1970s was the Conway and Mead Revolution (c. 1978), a structured design methodology which, for the first time, made custom ASIC capabilities more widely available to non-semiconductor companies. This meant that a really cost-sensitive, high volume design needing advanced capability would have one or more custom ASICs surrounding a CPU. Yet more SSI (and all MSI) gets absorbed into the ASIC and system LSI's. Classic example: the Apple IIc and later the first Mac, which had the IWM chip that dealt with the floppy.

At the board level, surface-mount, once the exclusive province of military, space-borne, and very-high-volume consumer electronics like calculators, and as mentioned, came to see wider adoption in computer systems as well beginning in the later 1980s. Over time, DIP and other though-hole devices became less convenient and cost-effective.

You can see over time the general shift in the market, with each level of integration supplanting earlier, less-dense technology. The market share, if not outright volume, SSI logic has become ever smaller, with SSI increasingly left nibbling at the margins as a supporting player rather than a central, enabling technology in itself.

Side note: the standard corner pin placement used for TTL adds lead inductance to Vcc/Vss, reducing the device performance. For a time there were (and maybe still are) center-power DIP parts to improve this.

Fast forward to now.

We live in an era where big SoCs, microcontrollers and other large chips dominate most designs. The remaining large off-chip datapaths are either serial (serdes) or DRAM. Even the glue-logic stuff previously done in PLDs has disappeared, all hoovered up by Moore's Law and the march for ever-higher integration, higher speed, and lower cost.

As a consequence,

  • Through-hole devices of all kinds, including SSI logic, are largely obsolete, except for hobbyist, prototyping and low-volume specialty work.

DIP logic of any kind isn't cost-effective. Yes, you may love your proto board, but the industry doesn't.

  • MSI and LSI have largely vanished.

Almost all the datapath elements as well as glue logic are integrated into the big chips, or implemented in large programmable devices like FPGAs. Not everyone wants to be Ben Eater and 'make' their own CPU from TTL.

Yet despite the seemingly decreased relevance of SSI logic, a need persisted to deal with small stuff at the margins: drive an LED here, 'AND' a couple of control signals there. However, these system-level odds and ends now happen on space- and cost-constrained, and most importantly, surface-mount boards.

A market thus emerged for 'tiny' surface-mount glue logic that served to deal with these marginal SSI cases. (ed note: TinyLogic is a trademark of On Semiconductor.) The remaining SSI players in the market pivoted to supply this need.

A DIP SSI function - be it a single or multi - would not only take more space, but would introduce a need to hand-solder or wave-solder the board. So the logic needs to be small as possible, it needs to be SMT, and as cheap as possible. This favors a single-function SMT IC.

Besides logic, level shifting is another case that shows up in small-footprint single- or 2-gate glue logic. This is another system-level problem that is often not dealt with by those big, highly-integrated devices that also want to use ever-lower I/O voltages.

Yet, in both cases there's rarely a need for more than one or two functions in a package. The emphasis is instead on tucking a bit of gate-level glue into an otherwise-packed SMD board to patch an issue that the big chips couldn't or didn't deal with. (This, too, is also where discretes still come into play.)

I should also mention another very useful at-the-margins 'tiny' solution: Silego (now Renesas) GreenPAK. This is a family of small FPGA-like devices that include logic, flip-flops and some mixed signal stuff, in very tiny packages. For example I used one to create a rest + PWM fan controller + thermal monitor for an SoC that didn't have these features, in a very tiny 20-pin LCC package.


There never was single logic gate through hole versions of standard chips, they always came in standard packages and pinouts and they were fully utilizing the available pins with one set of supply pins - which typically meant something like dual SR flip-flop, quad NAND gate or hex inverting buffer.

And most of the time, only a single gate would not have been used. If you needed just a single logic gate for your whole project, you likely would not even put a single logic gate but implement the logic with diodes or transistors which you would likely have already on your PCB so a few more won't be that expensive.

It would not have been economically viable to have single gates in one package, or otherwise they would have existed. It was more economically viable to think what kind of logic you need and for what purpose, and then buy the chips and utilize them in a way that in the end performs all the logic operations you need, as the boolean logic equations can always be rearranged to use diffent gates to implement the same function.

So having more chips that are smaller will end up having more space, as each chip needs supply pins anyway, so it is more efficient to pack a lot of gates into one package.

If you are prototyping, you prototype with what you have, and the prototype will be larger and more expensive than the end product with less chips. For example, you can build a prototype for an integrated chip out of discrete logic chips before committing to manufacture an IC. The prototype for a single IC could have been one or multiple PCBs filled with standard logic chips, even if the end product is a chip with 50 to few hundred pins.


When digital logic became really widespread (in the '70s) with the TTL technology and all its families (with CMOS technology starting to see significant adoption), the chips were relatively expensive and very few applications required single gates.

So it was commercially more convenient to package multiple gates in a single IC sharing the same supply terminals. In fact packaging was a significant part of the cost, where adding one or two gates on a tiny silicon chip didn't add much to the cost of the IC, even if the gates were not used.

Keep in mind, most common single gates (having 1, 2 and 3 inputs) would have required 3, 4 and 5 pins respectively. So you would need to standardize 3, 4 and 5 pin packages, when standard DIP packages with 8, 14 and 16 pins had already been standardized for analog chips (e.g.: op-amps, audio amplifier chips).

So it was much easier to reuse already standardized packages, and since the pin count allowed, pack more gates in the same chip. And since at the time digital logic was heavily driven by digital computers, there was a tendency to fit multiple of 4 gates in a chip (that was the era of 8 bit computing).

Single-gate chips were never made until CMOS became the dominant technology and some manufacturers began selling parts such as the 1Gxxx CMOS gates.

However they had no big success and we were already in the SMD era. Together with the fact that even if you need a single gate today it is easy and inexpensive to add a tiny SMD IC with multiple gates in it, that made sure that single gate chips never took off, let alone in TH packages (I'm not even sure they had ever been manufactured as through hole).

Moreover, nowadays when most complex digital logic is implemented with MCUs or FPGAs, it is rare to need just a single gate. What you really do is just change the programming of the MCU or the FPGA and you are done with it.

Chips with individual gates nowadays are mostly used as buffers, bus interfaces or line drivers, so you usually need them in multiples of 4 or 8, so it makes still less sense to manufacture single-gate devices.

If a single gate is really needed, and the application is not demanding, it's so special a case that many times it's more convenient to design your own with a tiny SMD mosfet with some diodes (sort of ad-hoc DTL logic).

OTOH, for high-end applications where a single gate is really needed the cost is not an issue, so using just one of those inside a multiple-gate chip is still easier and cheaper.

Moreover keep in mind that TH technology for digital logic has been obsolete for years now, surviving just in schools and labs for easy breadboarding during training.

Many manufacturers today have completely expunged TH packages from their digital products portfolio. I think only Texas Instruments (of the major players in the field) still manufacture standard logic families in TH packages today.

For example, this is an excerpt of the 2012 datasheet of the standard hex inverter chip 74HC04 from Nexperia (NXP at the time):

NXP 74HC04 - 2012

where the DIP14 package was still available. In the 2023 datasheet of the same chip now you find this:

NXP 74HC04 - 2023

The DIP package has disappeared and there are more SMD package options.

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    \$\begingroup\$ I don't remember seeing any analog devices like the u747 and LM101op amps in DIP packages in 1970. They came in 8-pin metal cans. \$\endgroup\$
    – SteveSh
    Mar 22 at 12:31
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    \$\begingroup\$ @SteveSh I didn't say in 1970, I said "in the 70's". \$\endgroup\$ Mar 22 at 12:40
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    \$\begingroup\$ @SteveSh in 1975 Texas Instruments already sold chips in DIP packages, as one coud see in its 1975 logic databook. \$\endgroup\$ Mar 22 at 12:42
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    \$\begingroup\$ I need to hedge my comment a bit. I have a 1973 Fairchild Linear Integrated Circuit catalog in my possession. The 'uA741 did have the option of a 14-pin DIP, part number 741ADM. Even earlier op amps like the '702 came in 3 package types - 8-lead metal can, 14 pin DIP, and a 10-lead flat pack. \$\endgroup\$
    – SteveSh
    Mar 22 at 13:19
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    \$\begingroup\$ @SteveSh Technology history is fun! :-) \$\endgroup\$ Mar 22 at 13:20

There is one single logic gate available in a 14-pin DIP package.

I present to you the 74LS30 8-input NAND gate:

enter image description here

(Image excerpted from futurlec.com/74LS/74LS30.)


If you go on Digikey and search for "Gates and Inverters" and filter on "In Stock" I see 345 items. So, through hole gates are still sold there.

If you filter on 8 pin packages, there are three items (AND and NAND gates). There are two gates per package. Given that you also need two power pins, you would need at least 5 pins for one gate. Though 6 pin DIP does exist, it's not common in my experience. The smallest common package size that has at least 5 pins is the 8 pin DIP.

If you filter on Number of Circuits = 1, you find 26 items. They are all NAND gates, with either 8, 12, or 13 inputs. So apparently, they do sell single NAND gates. They just have more than 2 inputs.

Keep in mind that there has been a worldwide microchip shortage for the past few years. So, the fact that you can't find something in stock right now doesn't mean they don't make it anymore. They could actually just be temporarily out of stock, and it might appear back in the coming months or years.

I had plenty of times we wanted to order a part in 2022 and the ship date showed as 2023 or 2024. In which case we found an alternative rather than waiting.


They were used in the block I Apollo Guidance Computer

There were two versions of the Apollo Guidance Computer (AGC). The first version was built with singular 3-input NOR gates, in T0-47 cans with through-hole leads:

Block I NOR gate


On January 27, 1967, one copy of this computer was on the launchpad with astronauts Gus Grissom, Ed White, and Roger Chaffee when the command module caught fire, killing all three astronauts. As a result of the distaster, the mission was named Apollo 1, and the AGC was redesigned along with the rest of the command module.

The old design was called "block I". The remaining 3 block I AGC units flew into space on the uncrewed test missions Apollo 3, 4, and 5. Thus, the ICs asked in the question have been to space!

The new design was called "block II". It used dual 3-input NOR gates in a flat pack, so they do not qualify for the question. However, they are more widely known, as they were the ones that were used on all of the crewed Apollo missions.

Both designs also used IC sense amplifiers for the core memory, in metal cans with through-hole leads. However, it's arguable whether these qualify as "logic gates".

Also of note is that the Saturn launch vehicle used in Apollo had its own computer. This computer was built by IBM out of modules that look like ICs. However, the inside of these modules are tiny printed circuit boards with soldered components:

outside module

inside module

The AGC is credited for keeping early IC manufacturers in business. Because the block II AGC no longer used single logic gates, they were no longer economically viable.

  • \$\begingroup\$ Interesting piece of history. Thanks for sharing. I'm gong to venture a guess that the reason for the TO-47 style metal can package was because of the need for hermiticity, which is provided by the glass seals on the leads? \$\endgroup\$
    – SteveSh
    Mar 25 at 1:13
  • \$\begingroup\$ @SteveSh: Discrete transistors at that time were in metal cans, and had been used for the Gemini Digital Computer, so that packaging technology was already proven. I'm not sure if any other device previously used 8 pins on a metal can, but certainly there had been vacuum tubes and relays that had that number of pins. \$\endgroup\$
    – DrSheldon
    Mar 26 at 17:36
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    \$\begingroup\$ Op amps, such as the Fairchild u702, u741, and the NSC LM101A came in that same 8-pin metal can. The u747 (a dual op amp) came in a 10-pin metal can. Westinghouse's Molecular Engineering Division (now Northrop Grumman's Advanced Technology Laboratories) in Elkridge, MD had many devices in 8 and 10 pin metal cans. I don't recall seeing anything there in 1966(?) in any other kind of package. \$\endgroup\$
    – SteveSh
    Mar 26 at 18:12

If you need only a gate or two, it doesn’t matter much whether it’s SMD or through-hole, convenience-wise, right?

But typical applications of gates in gate-oriented “discrete” logic designs call for a lot of them. So 14-16 pin packages are not wasting space - you needed those gates anyways. And when it comes to tiny chips that have few active devices and are just standard cmos process - the most expensive part of them is the lead frame and the encapsulation. The silicon is almost free, because it’s made at astounding scales in an automated manner, whereas through-hole packages are a pain.

So, using gates in small through-hole packages would be uneconomical when you need many. And when you need few, “wasting” a couple in a larger package - who cares? Or use the SMD ones.

I have made a few “retro” designs over the years just for fun - all of them having thousands of equivalent gates - and usually each module can have all the gates used up. Sometimes it took some creativity, but generally speaking if I need many gates, any gates you give in those DIPs get used up.

I have soldered a few large discrete through-hole transistor analog+digital designs, and let me tell you: I’d much rather have those transistors come in DIP packages than TO-92. Soldering hundreds or even thousands of TO-92s gets real old real quick.

So, if you need a sea-of-gates in through hole - you’ll hate single-gate packages almost immediately with any project scale past the most trivial.

And for discrete sea-of-gates retro projects: you really want a machine to populate the hundreds or thousands of gates needed, and do it cheaply. Small SMT packages let you keep the interconnect short and their placement can be easily optimized with any autorouter that optimizes autoplace. They leadless packages are so small that you can replace 80s vintage gate arrays with a couple thousand gates on a 100x160mm Eurocard that any major PCB vendor will populate for you.

As for the waste of space argument: if you’re using through-hole, you don’t care about space anyway. You can fit dozens of single SMT gates where a single DIP-14 would sit. So, if you needed space to be small, and assembly costs low in volume, you’d have been using SMT anyway.


Why are there no single gates in DIP-4 package for NOT, DIP-6 package for other functions, or at least triple NOT and dual AND/OR/etc. in DIP-8 package in order to keep a common package?

The main point of using single gates is to save board space when you just need one gate for glue logic, voltage conversion or buffering.

A tiny SMD package like SOT-23-5 uses much less board space than a DIP.

Therefore, making single gates in DIP packages would defeat the point...


Noting that Dual In Line (DIL) plus variants such as Dual In Plane (DIP) encapsulation were adopted almost universally for TTL and later logic families, but IC history didn't start there.

For example, https://www.ourcomputerheritage.org/Minicomp/Ferranti_intro_and_Argus_combined_Arial.pdf describes Ferranti "Micronor" logic used in the Argus 400 and 500, and explicitly says that its outline was TO-5 (even if its connection footprint had significantly more leads) and at least in early devices had one gate per can.

See e.g. the photo at p15 of https://www.sba.unipi.it/sites/default/files/2015_05_29_08_44_132.pdf noting that if those cans contained individual transistors there would almost certainly be more passive components on the board.


Wow, I see there are some other geezers around here, just to geez some more lookin in my '76 TTL data book that I got as a young freshout there were/are official 74xx single gate packages. 7430 -- 8 input nand gate 74s133 -- 13 input nand gate -

It looks like 7340 dips are still around, so just tie the extra inputs appropriately and wala! you have your single gate through hole.

They did come in 14 or 16 pin dips though. So while they are "single gate" packages I'm perhaps cheating a bit


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