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I am trying to create a negative voltage source with a high-side MOSFET using another voltage source which is 4 V higher than the MOSFET's drain voltage.

In the schematic Q3's drain has 12 V and gate sees 16 V pulses. In this design, is 16 V enough for driving Q3 or will it need a higher voltage on the gate?

Feedback is going to an MCU and I used a voltage divider. In the worst case the feedback sees 12 V which is too much for feeding back to the MCU and in the best case feedback sees 1.09 V. Is there a better way to return feedback to the MCU from a negative voltage source?

Schematics

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  • \$\begingroup\$ You must drive Vgs, not Vg. This driver will not allow source to fall below -3V or so. The 16V supply isn't really necessary as a bootstrap supply can be used, but the negative swing must be solved. Also, +12V will need a large bypass capacitor to GND. \$\endgroup\$ Commented Mar 22, 2023 at 17:39
  • \$\begingroup\$ I already have a 16V source in the project, so instead of bootstrap driver i want to use 16v source if it solves the problem. D1, L1 and C1 are in inverting buck-boost configuration, when Q3 opens source reaches 12v and inductor stores energy and releasees it into C1 as soon as Q3 closes. This circuit should easily go below minus 20Volts. I dont expect source to go below 0 volts, actually i need source to be 12volts as soon as Q3 opened. About vgs, With 16V on the gate and 12V on the drain there will be 4V difference does it meant that i have 4V vgs? \$\endgroup\$ Commented Mar 22, 2023 at 19:30
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    \$\begingroup\$ You seem to have confused the meaning of "open" (high resistance) and "closed" (low resistance, in this case Rds(on))? When Q3 turns off, L3 discharges into -12V through the diode, by pulling the source below GND. Therefore Vg must go to -12V as well. \$\endgroup\$ Commented Mar 22, 2023 at 19:37
  • \$\begingroup\$ Does it mean that 16v gate driving voltage is more than enough? if source goes below gnd lets say -10v, then Vgs will be 16- -10 = 26v \$\endgroup\$ Commented Mar 22, 2023 at 19:48
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    \$\begingroup\$ If source drops to -10V, and Vg is driven positive, Vgs will be 26V, and the transistor will be hard on, dumping about 100A from +12V to whatever's holding it at -10V. Do you understand basic MOSFET operation..? \$\endgroup\$ Commented Mar 22, 2023 at 21:45

2 Answers 2

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Sadly, 16V is not high enough, but neither is 0V low enough for Q3's gate.

Q1 is supposed to drive Q3's gate high, but its base-emitter junction drops 0.7V (it's operating as an emitter follower, don't forget), leaving only 15.3V at the gate, for \$V_{GS} = 3.3V\$. Q3 could require \$V_{GS}=4V\$ to just begin switching on. To switch it on and pass significant channel current (without dropping significant voltage between drain and source), I expect you'll need much more than 16V at its gate.

Fig. 1 on page 3 of this datsheet shows you what voltage \$V_{DS}\$ you can expected the channel to have at various \$V_{GS}\$ and channel currents. For instance, looking at the curve for \$V_{GS}=4.5V\$, you can see that at 3A channel current, you lose 0.4V. I think you should be aiming for \$V_{GS}=6V\$ at least for this application, which implies a gate potential of 18V.

The worst issue you will face is that by using an N-channel MOSFET high-side, you are operating it common-drain, as a source follower, whose source is never further than 4V below the gate; \$V_S = V_G-4V\$. You bring the gate down to +0.7V (not 0V, again because Q2 is an emitter follower), and Q3's source gets clamped to a minimum of -3.3V. This is bad, since the source (cathode of D1) must be free to swing to -12V in order to charge C1.

You must therefore drive Q3's gate with potentials +18V and -8V or so, which is quite the dilemma. The NMOS solution in the answer by "Kuba hasn't forgotten Monica" can be simulated; watch how gate potential swings between these extremes. The easiest solution to both of these problems is to use a P-channel device, which you can switch with 0.7V and +11.3V.


Update: I made it sound like PMOS answers all the problems, but be aware that in this setup it's easy to get \$V_{GS}\$ to exceed ±20V, which is a common maximum for many MOSFETS. Either make sure you use a device which can handle ±24V between gate and source, or take measures to protect that gate.

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I see several problems:

  1. Gate drive needs to be referenced to output voltage, i.e. the low level of the gate voltage must follow the negative output level. Otherwise, the mosfet will stop turning off when the output goes past -3V or so.

  2. +16V is not a high enough gate drive, given the Vth spread. A bootstrap voltage generator is needed.

  3. The gate driver you propose is so slow that it will cook the mosfet due to conduction losses. Use an IC gate driver, or a suitably fast discrete solution (see below).

  4. There's no inductor current sense. The upper duty cycle limit will have to be rather controlled based on the output voltage. When V(OUT)≈0V, only rather tiny duty cycle will let the inductor current cross 0 - otherwise the inductor will saturate due to runaway positive current.

    The D.C. has an upper limit that goes up as the output voltage goes down. That's a hard limit to avoid inductor current runaway. The duty cycle can then be reduced as the voltage control loop gains control.

  5. Whatever efficiency savings might have been there by using an NMOS were obliterated by poor gate drive. Of course, it's not as if a PMOS can have slow gate drive either, just that the gate voltage swing would be smaller, so there would be less gate switching losses.

NMOS Variant

Tirst' let's address the circuitry around the switch, and then we'll tackle the gate driver.

schematic

simulate this circuit – Schematic created using CircuitLab

The boost voltage relative to ground is the sum of the difference between the input voltage and output voltage - just shy of 24V.

Now, we need a good gate driver. The one you got is very slow and will make the mosfet run very hot. The driver below produces ≈50ns edges into a 2nF gate capacitance. The input is 3.3V CMOS logic.

Q5 and Q6 drive away the stored base charge, since Q7 and Q8 saturate.

schematic

simulate this circuit

This gate driver's low output level must be below about 0.5V, and the high level must be above about 2.5V. Within these limits the driver will work with other voltages too, e.g. 0V-12V, etc.

PMOS Variant

To save on gate switching losses in M1, it should be a PMOS - then we get rid of 16V and BOOST circuitry, and the gate driver's output levels change to 0V-12V:

schematic

simulate this circuit

And the gate driver:

schematic

simulate this circuit

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  • \$\begingroup\$ Thank you for your answer, it is realy very descriptive. I will go with pmos as it will be more easy to drive it. \$\endgroup\$ Commented Mar 23, 2023 at 10:20
  • \$\begingroup\$ @yusufşahin You might as well use a gate driver chip, unless you really want to build one out of discrete transistors. Although transistors are usually easy to get anywhere, but genuine gate drivers have to be ordered from a major distributor or else they likely are fakes. You definitely want to test the gate driver with a 2nF capacitor load before attaching any mosfets to it. Then you need an oscilloscope and use a 5k potentiometer in place of R2 and see when the output looks best. And all of this has to go on a well laid out PCB. Solderless breadboard won’t work properly. \$\endgroup\$ Commented Mar 23, 2023 at 11:28
  • \$\begingroup\$ Let me know whether you plan to lay out a PCB or would like to see how to assemble a prototype properly without a PCB. And: ask a separate question where you share your control algorithm, ideally with some code, and get some opinions on how feasible it is not to turn the inductor into a charcoal briquette :) You can then let us know what MCU the code is for and perhaps someone will review it, run it on hardware, and give some hints :) \$\endgroup\$ Commented Mar 23, 2023 at 11:30
  • \$\begingroup\$ Also there may need to be a 330ohm..1k resistor between the base of Q5 and 12V, and base of Q6 and ground. Also, with actual mosfet attached, verify the integrity of the gate waveform, and add a small series resistor if needed, say 5-40ohm. May not be needed with good layout. \$\endgroup\$ Commented Mar 23, 2023 at 11:32

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