MOSFET decapsulated

MOSFET Connection

The above are physical look of a decapsulated MOSFET and the diagram connection between the source (S), gate (G), drain (D), and the body. Both of them are kind of N-MOSFET. If you want to see how the decapsulation is done, you may click here, while the second picture explaining how MOSFETs work, link is here.

I would like to separate the body from the source, the gate will be controlled by own power separate or independent than the controlled power (the Vds.) By so, I will be able to control AC current as the controlling gate is not changed.

How can I separate the body from the source so I can feed power to the gste-body with a separate, independent power source?

  • 2
    \$\begingroup\$ You can't as the silicon die itself doesn't have a separate body connection. \$\endgroup\$ Mar 22, 2023 at 20:30
  • \$\begingroup\$ This isn't really done (although there are several regular posters here who love to remind everybody that MOSFETs are 4 terminal devices). Perhaps an opto-isolator can achieve what you want. \$\endgroup\$ Mar 22, 2023 at 20:46
  • \$\begingroup\$ @evildemonic opto is a type of NPN transistor which the base is controlled with optic. So, current only flow one direction. \$\endgroup\$ Mar 22, 2023 at 20:55
  • \$\begingroup\$ @JonathanS. very sad. I thought that it can be done. \$\endgroup\$ Mar 22, 2023 at 20:56
  • 1
    \$\begingroup\$ @AirCraftLover The TLP3555 is one, sure. There are loads, though. And I'm including triacs as a type of thyristor, even if that's maybe not technically correct--triac optocouplers are common. \$\endgroup\$
    – Hearth
    Mar 23, 2023 at 4:38

1 Answer 1


Sure, no problem.

For reference, here is a cross-section of a typical trench MOSFET structure:

Trench MOS diagram Source: Cross section of a trench gate vertical DMOSFET | ResearchGate

Notice the "Source / Body metal" contacts both P+ and N+ surface regions, shorting them together. The P+ region in turn connects to the P-type body, under the surface.

You must remove the source metallization, and rearrange it so that the P+ and N+ connections can be made separately. You will need:

  • Bare die or decapsulated device. Note that laser decapping as shown in the video will not work, as the die is utterly destroyed in the process. Typically hot fuming nitric acid is used for this; the lead frame is destroyed in the process, and the chip will need to be mounted onto a carrier for subsequent processing, and eventually repackaged.
  • Removal of original metal and passivation layers. We must access the bare silicon surface. This may possibly be done by mechanical means (polishing), chemical etching, or both. Hydrofluoric and hydrochloric acids would be typical for etching the SiO2 and Al layers respectively. Do not remove the gate (if metal was used for it).
  • An extremely precise analysis of the surface doping is required, so as to reverse-engineer the manufacturer's patterning. A polarized optical microscope is used for this, I believe, but if the feature size is quite fine, electron microscopy may be necessary, and other more esoteric means to determine doping type.
  • Once the N+ and P+ regions have been determined, sputter/evaporate an isolation layer of SiO2 onto the surface, then photo-image and etch holes into it, and finally apply and etch metallization to make contact with the respective regions. You will have to make the source contacts first, probably, to minimize added resistance.
  • Apply another layer of SiO2 and make the body connections. Holes will have to be etched down to the P+ regions (if these are quite deep, use RIE?).
  • Finally make connections to the gates, in the same way. It's probably worth reproducing the interconnect pattern the original manufacturer used, to maintain good performance (low gate and source resistances).
  • A final passivation layer of SiO2 may be desirable; etch to leave openings for wire-bonding to the source, body and gate terminals. (Drain is on the backside, which should still be coated with solder or other die-attach material.)

The approximate budget for buying the necessary equipment new is probably in the several $10M range. You may be able to get assistance from a well-equipped university or laboratory for a somewhat smaller budget.

Notice that source and body are adjacent highly-doped (meaning of the "+") regions, therefore the breakdown voltage between them will be extremely low, perhaps a few volts. You will have very little usable range of the "back gate"; perhaps not even enough to induce conduction while holding Vgs = 0. Note that any body-diode current must flow from drain to body, so the body connection must be as robust as the source terminal is normally; any inductance between the two terminals -- relevant when current reverses through the device -- will likely blow it out as S-SS breakdown occurs.

Overall, it doesn't seem too useful a device, but I suppose it is technically possible.

Disclaimer: I haven't designed any semiconductors before, or worked in the specific field at all; I just use them, and know some things about them. This is of course a vast oversimplification of an extremely intricate process, and probably contains factual errors. On the upside, the required budget will more than cover hiring a few PhDs to review and manage the process.

  • 1
    \$\begingroup\$ Removal of the metal runs the risk of trenching the silicon underneath too, which will ruin your contact resistance (as you can easily etch through the high-doped surface layer). You'd need to spend some additional money hiring a fab engineer who knows what they're doing and buying a few hundred parts for them to experiment on to figure out exactly how long to do the wet etch to avoid trenching. \$\endgroup\$
    – Hearth
    Mar 23, 2023 at 3:01
  • \$\begingroup\$ Fortunately, spare parts are the cheapest part of this whole endeavor! \$\endgroup\$ Mar 23, 2023 at 4:26
  • \$\begingroup\$ Hiring a fab engineer (who are pretty highly-paid, as I understand it) for the couple months it would take to get the process under control is the real expense there, yeah. \$\endgroup\$
    – Hearth
    Mar 23, 2023 at 4:42
  • \$\begingroup\$ Is it still MOSFET? \$\endgroup\$ Mar 23, 2023 at 9:34
  • \$\begingroup\$ The plan would be not to touch the gate or gate oxide in the process, and keep all the underlying material (epitaxy + drift region / substrate) the same. So yes, still MOSFET. \$\endgroup\$ Mar 23, 2023 at 13:22

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