EFT generator circuit

Question

I am simulating a circuit to model the EN 61000-4-4 waveform for electrical fast transients using LTspice. The idea is to have the generator for some in house testing.

After a lot of back and fourth with @Andy aka and @Tim Williams (special thank you to both of them) I decided to use the schematic of the generator provided by the test standard IEC61000-4-4.

After a few hours of figuring out the parameters I have somewhat of a satisfactory simulation.

This is my circuit, I am using an ideal switch and here is where my problem is. I would like to have some help picking a good switch in order to get close to the standard's requirements. In addition, if there are any suggestions to be made regarding my circuit, I welcome them. The following probing nodes have been added: EFT_output / Energy_storing_capacitor / Pulse

Here are the results the probed nodes:

1. Energy_storing_capacitor, the capacitor has an initial voltage of 1000V

The switch starts conducting with no delay :

This is the output voltage, the rise time is 221ps due to the fact it is an ideal switch

As we can see the amplitude satisfies the requirements of the standard.

Here is what the output looks like if an inductor is added

Here is the circuit with said inductor :

Answer 1

Here is an idea to solve this problem. I will gladly accept feedback, especially from the people that have worked with me so far (@Andyaka & @Tim Williams).

Due to the lack of inexpensive high voltage high speed power semiconductors on the market, trying to build a the power semiconductor switch using low voltage power switches that are easily found on the market maybe a solution. Since the big challenge is to achieve the 5ns rise time (or close to that...) specified on the standard for the output pulse, the possibility of using a high power switch topology with a Flyback power converter topology as the gate driver.

Here is the circuit :

There are five operational stages of a proposed switch design. In the first stage, energy is stored in the primary inductor when the driver switch is closed. In the second stage, the switch is opened and energy is sent to the gate input capacitance until the gate voltage reaches the zener voltage. The third stage occurs when the secondary inductor current continues to flow through the zener diode and load resistance, with the switch remaining closed. The fourth stage begins when the secondary inductor current is unable to maintain the load resistance voltage at the zener voltage, causing the switch to open after a fixed on-time. The fifth stage has no current flow.

Here are the simulations of the circuit :

here is the profile of one pulse : Lowest voltage is 7V, highest voltage is 250V. To measure the rise time, we have 0.1*Vpeak = 25V and 0.9*Vpeak= 225V.

We can see that the pulse respects the standard as the rise time is just below 5ns, but of course this is an ideal case since there are no parasitics included,etc.