I am simulating a circuit to model the EN 61000-4-4 waveform for electrical fast transients using LTspice. The idea is to have the generator for some in house testing.

After a lot of back and fourth with @Andy aka and @Tim Williams (special thank you to both of them) I decided to use the schematic of the generator provided by the test standard IEC61000-4-4.

enter image description here

After a few hours of figuring out the parameters I have somewhat of a satisfactory simulation.

This is my circuit, I am using an ideal switch and here is where my problem is. I would like to have some help picking a good switch in order to get close to the standard's requirements. In addition, if there are any suggestions to be made regarding my circuit, I welcome them. The following probing nodes have been added: EFT_output / Energy_storing_capacitor / Pulse enter image description here

Here are the results the probed nodes:

  1. Energy_storing_capacitor, the capacitor has an initial voltage of 1000V enter image description here

The switch starts conducting with no delay : enter image description here

This is the output voltage, the rise time is 221ps due to the fact it is an ideal switch enter image description here

As we can see the amplitude satisfies the requirements of the standard. enter image description here

Here is what the output looks like if an inductor is added
enter image description here

Here is the circuit with said inductor : enter image description here

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    \$\begingroup\$ Now is the real tricky bit. Converting the switch into a lump of silicon that can produce a rise time of circa 6 ns is difficult. Maybe you should also add a waveform of one single pulse so that we can look at the rise time. \$\endgroup\$
    – Andy aka
    Mar 23 at 20:27
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    \$\begingroup\$ I agree, I thought getting the output voltage amplitude is hard... I wish I started with the circuit diagram proposed by the standard earlier... (you were right all along) Yes I can add the waveform here. \$\endgroup\$ Mar 23 at 20:39
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    \$\begingroup\$ Dimitar, can you instead focus on the rise time of the pulse so we can see it in detail. Also, there are no axes scales so it's got no use as information. \$\endgroup\$
    – Andy aka
    Mar 23 at 21:18
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    \$\begingroup\$ @Andyaka Rise is probably about zero because an ideal SPICE switch was used. Yes, would like to see axes, and which node is being measured. And a label on the node so we can tell which it is. Note that we can't tell that 50/1000 ohm amplitudes have been respected, but the circuit should at least be doing something along those lines so that can be addressed more fully later and if necessary. \$\endgroup\$ Mar 23 at 21:23
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    \$\begingroup\$ Sorry yes you are totally right... I will update the screenshot. Unfortunately, since the switch is ideal the rise time is in the picoseconds range \$\endgroup\$ Mar 23 at 21:24

1 Answer 1


Here is an idea to solve this problem. I will gladly accept feedback, especially from the people that have worked with me so far (@Andyaka & @Tim Williams).

Due to the lack of inexpensive high voltage high speed power semiconductors on the market, trying to build a the power semiconductor switch using low voltage power switches that are easily found on the market maybe a solution. Since the big challenge is to achieve the 5ns rise time (or close to that...) specified on the standard for the output pulse, the possibility of using a high power switch topology with a Flyback power converter topology as the gate driver.

Here is the circuit : enter image description here

There are five operational stages of a proposed switch design. In the first stage, energy is stored in the primary inductor when the driver switch is closed. In the second stage, the switch is opened and energy is sent to the gate input capacitance until the gate voltage reaches the zener voltage. The third stage occurs when the secondary inductor current continues to flow through the zener diode and load resistance, with the switch remaining closed. The fourth stage begins when the secondary inductor current is unable to maintain the load resistance voltage at the zener voltage, causing the switch to open after a fixed on-time. The fifth stage has no current flow.

Here are the simulations of the circuit : enter image description here

here is the profile of one pulse : Lowest voltage is 7V, highest voltage is 250V. To measure the rise time, we have 0.1*Vpeak = 25V and 0.9*Vpeak= 225V. enter image description here

We can see that the pulse respects the standard as the rise time is just below 5ns, but of course this is an ideal case since there are no parasitics included,etc.

  • \$\begingroup\$ @Andyaka and do you have some comments? \$\endgroup\$ Mar 28 at 17:22
  • \$\begingroup\$ @TimWilliams and do you have some comments? \$\endgroup\$ Mar 28 at 17:22
  • \$\begingroup\$ You can save all that effort and not lose DC coupling by just using a TC4420, dude \$\endgroup\$ Mar 28 at 17:23
  • \$\begingroup\$ I do not understand your point? \$\endgroup\$ Mar 28 at 17:27
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    \$\begingroup\$ A flyback circuit can not supply reliable and stable gate voltage independent of gate charge (which varies from part to part) and is rate limited by the coupling factor (you will be hard pressed to find "k L1 L2 1" in practice). A gate driver is made specifically to drive gates, and they do quite well at it; that's why they make them. \$\endgroup\$ Mar 28 at 17:30

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