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Suppose I designed a single supply op-amp, with \$V_{dd} = 1.8\mathrm{~V}\$, and \$V_{ss} = 0\mathrm{~V}\$. Furthermore, I designed the op-amp such that \$V_{out,max} = 1.3\mathrm{~V}\$ and \$V_{out,min} = 1\mathrm{~V}\$.

I then connected the op-amp in unity gain configuration, with a voltage source \$V_{cm}\$ supplied to the non-inverting terminal. I'd like to find the gain error for different values of \$V_{cm}\$.

Single supply op-amp connected in unity-gain configuration with a voltage source on its non-inverting terminal

I suspect that the DC gain error is \$0\mathrm{~V}\$ when \$V_{cm}\$ is equal to the output common-mode i.e. \$(1.3 - + 1) / 2 = 1.15\mathrm{~V}\$, which would yield a graph as follows:

Voltage error graph for the buffer.

For the ideal unity gain buffer we just get the line \$V_{out} = V_{cm}\$, However for the actual op-amp we get the line \$V_{out} = \frac{A_{OL}}{1+A_{OL}}V_{cm} + V_0\$, where \$A_{OL}\$ is the open-loop gain, and \$V_0\$ is the y-intercept. If I then wanted to find the DC gain error at \$1.25\mathrm{~V}\$ as shown, would this be the correct approach?

On the diagram the annotated \$V_{error}\$ is the voltage error at \$1.25\mathrm{~V}\$ and so the DC gain error would be \$V_{error}/1.25\mathrm{~V}\$. If this is incorrect, could someone clarify the correct way to approach this problem?

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  • \$\begingroup\$ You might be missing the point here. At dc, the biggest error will come from the input offset voltage and bias currents so, what is the motivation for this question? \$\endgroup\$
    – Andy aka
    Commented Mar 24, 2023 at 13:01
  • \$\begingroup\$ @Andyaka You may be right, but if we assume that the offset voltage and bias currents offest are zero, then does my analysis hold? \$\endgroup\$
    – Jonah F
    Commented Mar 24, 2023 at 17:02
  • \$\begingroup\$ @JonahF Where did your non-ideal equation come from, what Aol you used, and why? Assuming Aol is in the order of 1e5, the Vout will still be extremely near to Vin. \$\endgroup\$
    – Justme
    Commented Mar 24, 2023 at 17:10
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    \$\begingroup\$ Great figures, by the way! \$\endgroup\$ Commented Mar 24, 2023 at 17:23
  • \$\begingroup\$ @Justme it comes from the fact that the closed loop gain of an op-amp in a buffer configuration is \$A_{OL}/(1+A_{OL})\$. Therefore, the graph of \$V_{CM}\$ against \$V_{out}\$ where \$V_{CM}\$ is the voltage applied to the non-inverting terminal of a buffer is a straight line with gradient \$A_{OL}/(1+A_{OL})\$. For a dual supply op-amp, we expect this to cross the ideal line at the origin (\$V_{CM} = 0\mathrm{V}\$), but for a single supply it would look like the above (I believe)! Im trying to figure out where it would cross in the single supply case. \$\endgroup\$
    – Jonah F
    Commented Mar 24, 2023 at 17:43

2 Answers 2

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The specific answer to your question,

When is the DC gain error of a single supply op-amp zero?

For a non-ideal (less-than-infinite gain) op-amp, it is when Vout is zero. This unique condition only occurs when inputs V+ and V- are exactly equal, without any other influence. Further, for your follower configuration where V- = Vout, that happens only when V+ is zero, too.

As for your analysis, your focus on common-mode voltage is not quite on the right track. The gain error isn't due to the common-mode input voltage (although it can have influence, expressed as op-amp parameter Common Mode Rejection Ratio, or CMRR). It's instead due to the op-amp's limited, non-ideal gain.

See eq. 1.18, below, from this MIT OpenCourseWare handout: https://ocw.mit.edu/courses/6-071j-introduction-to-electronics-signals-and-measurement-spring-2006/resources/22_op_amps1/

enter image description here

With your follower configuration, R2 is zero and R1 infinity. You're then left with \$G = \frac {1} {1 + 1/A}\$ .

Assuming no other errors have influence (like input offset, or CMRR), any deviation from unity gain is due to the fact that \$A\$ isn't also infinite.

With the voltage follower, \$G\$ will always be less than one. Thus, a graph of Vout vs. Vin is expressed as a straight line slope of \$G\$, with an intercept at Vin = Vout = 0.

The error? For a given Vin, the difference between that line and if \$G\$ were equal to 1.

In your scenario, if you want the voltage error when Vout is 1.25V, use the non-ideal gain equation expressed above, plug in 1.25V for Vout and work backwards from that to arrive at Vin.

You can also fiddle with the algebra to solve for a required \$A\$ to achieve a target allowable gain error.

I've alluded to common-mode voltage having influence. Here's a related answer on that: On measuring the common mode gain of an op-amp using a simulator?

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  • \$\begingroup\$ So, what concerns me about this answer, is that - doesn't this only hold true for a dual-supply op amp? I have the specific problem of applying this to a single supply op-amp. Therefore, when you say the two lines intercept at Vin = Vout = 0V, wouldn't this actually be a mid rail i.e. 1.8v/2 = 0.9v in the single supply case. Or, perhaps more generally at the midpoint of the common mode? This is based on something my lecturer said, but I wasnt 100% sure about. \$\endgroup\$
    – Jonah F
    Commented Mar 25, 2023 at 0:27
  • \$\begingroup\$ No. an op-amp biased for single-ended operation will introduce this error since it has a bias point that is something other than zero. \$\endgroup\$ Commented Mar 25, 2023 at 0:37
  • \$\begingroup\$ and so, how do I explain this: imgur.com/a/JCYFhWH . What I am simulating is the sweeping of the voltage on the non-inverting input, and then plotting the difference between the output of the op-amp and input source. This error is 0 at around 850mV? Seems to show that the DC error is 0 when the input is at mid-rail. \$\endgroup\$
    – Jonah F
    Commented Mar 25, 2023 at 20:36
  • \$\begingroup\$ Without knowing what other things this op-amp is modeling it’s hard to say. Try to find a model that only has open-loop gain, but no other influences (input offset, etc.) Try the ‘ideal’ one in Falstad that lets you set the gain. \$\endgroup\$ Commented Mar 25, 2023 at 21:17
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So in this case you say that the amplifier outputs correctly when its output is between 1 and 1.3 volts. As drawn I assume a perfect opamp that is configured for unity gain so when Vcm (odd name for the input voltage) is between 1 and 1.3 volts the DC error will be zero. The plot of Vout vs Vcm should be horizontal at 1V for Vc below 1 V, horizontal at 1.3 for Vcm above 1.3 and have a slope of 1 connecting the (Vout,Vcm) points of (1,1), (1.3,1.3)

Input bias currents or offsets can't generate any error voltages in this circuit but if your opamp has an input error voltage that will have to be accounted for, and become your DC error, I believe.

Now as for the use of Vcm on the pos input. I normally think of a voltage labled Vcm as a common mode voltage applied to both pins. However in this case when Vcm is in the range of 1 to 1.3 volts it is the common mode voltage.

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