For traces that carry a static DC current, it's pretty easy to calculate the minimum trace width based on the required ampacity of the trace. However, I'm not sure what should be considered when sizing a trace for CMOS, TTL, etc.
For example, if you've got flexibility in the board stackup and can make the trace thinner or wider and still meet the impedance requirements, what are the reasons for making the trace wider/thinner?
Do different logic families require different considerations for trace widths?
Are there reasons not to make digital logic traces as thin as possible to allow higher routing density with less crosstalk?