Strange ADC readings

Question

I am using the ADC on an STM32F030F4P6 to read a battery voltage, usually between 4.2 and 3.5 V. The resistor divider is designed to reduce the voltage so that 4.2 V input becomes ~3.1 V at the ADC and 3.5 V becomes ~2.6 V. The analog reference voltage is 3.3 V.

I'm getting a strange, stable, reproducible result as shown in this graph:

I've verified that the voltage at the ADC pin is as expected (i.e. the resistor divider is working as intended).

The ADC calibration process is being run at boot as per the datasheet:

LL_ADC_Disable(ADC1);

while (LL_ADC_IsEnabled(ADC1)) {
}

LL_ADC_REG_SetDMATransfer(ADC1, LL_ADC_REG_DMA_TRANSFER_NONE);

LL_ADC_StartCalibration(ADC1);

while (LL_ADC_IsCalibrationOnGoing(ADC1)) {
}

LL_ADC_REG_StopConversion(ADC1);

WRITE_REG(ADC1->ISR, LL_ADC_FLAG_EOC | LL_ADC_FLAG_EOS | LL_ADC_FLAG_OVR | LL_ADC_FLAG_ADRDY | LL_ADC_FLAG_AWD1);

LL_ADC_EnableIT_EOS(ADC1);
LL_ADC_Enable(ADC1);

// wait for VREF to stabilize
for (volatile uint32 i = LL_ADC_DELAY_VREFINT_STAB_US * (SystemCoreClock / 1000000U); i != 0; i--) {
}

// wait for adc ready
while (!LL_ADC_IsActiveFlag_ADRDY(ADC1)) {
}

I've taken multiple readings and the results are always the same. I'm using 12 bit resolution and sampling for 13.5 cycles. The results are the same if I sample for longer (e.g. 239.5 cycles).

Is this expected? I understand that the ADC is non-linear to some extent and that the error is dependent on where in the capacitor ladder the voltage is. Is this what I'm seeing here?

Or is the 1 nF capacitor interfering in some way? I added it to reduce the induced noise on the power rail when the ADC was active.

[Edit]

So, the datasheet says N/A for the impedance when using 239.5 cycles but... I suspect 3 MΩ is still too much. One thing I'm considering is using a really large capacitor, 1 uF, and just sampling the voltage very occasionally

Answer 1

While the issues discussed in other answers and comments (too high an impedance in the divider, perhaps sample rate) are real, I don't buy that they explain the observed behavior.

I think the effect is due to failure of the assumption "The analog reference voltage is 3.3V", as would occur if some linear regulator was used to power the MCU from V_BAT. That would explain the shape of the curve quite well.

Now that we have more schematic: that would be the case if the test is conducted with the LiPo1 battery (or a voltage source replacing it for test purposes) as the source of power: because the regulator U1 is linear, the 3V3 node would drop below 3.3V when V_BAT goes below about 3.8V (3.3V + drop of U1 + drop of Q1) and from then down the reading of the ADC would be off and too high, just as we see it!

A solution to this problem is to also measure V_REFINT, which is internally connected to the ADC_IN17 input channel, and apply a correction; as a first order approximation:

  V_BAT = (R₁₁ / R₁₂ + 1) * (ADC_PA4 / ADC_IN17) * 1.23V

It's possible to improve on this by replacing 1.23V by the factory-calibrated VREFINT_CAL.

And if we go to hardware, by lowering the impedance of the voltage divider (with the important drawback of a higher drain on the battery). It's possible to connect that divider only during measurement with more components, as in that answer.

Answer 2

I'm going to agree with @RussellH that the potential divider is problematic in that it represents a source impedance of over 500kΩ. The datasheet, in fig. 24, shows some internal shenanigans with a current source of 1μA, which when pushed or pulled through 500kΩ could produce errors over 0.5V. I am not sure, though, what that source is for, or represents.

As a first measure, try replacing resistors R11 and R12 for much, much lower ones (say 7.5kΩ and 22kΩ), and remove capacitor C11, which may also be causing issues. These changes are just temporary. If the problems go away, then you've identified them.

If lower values for R11 and R12 solved the issue, then obviously you must use lower values, but of course you wish to keep current in that divider as low as possible. However, instead of buffering the divider's output, which needs an op-amp and wastes more power, I think you could switch the divider on, measure, then switch it off again.

If you have a spare digital output, or can hijack one momentarily from an LED or something, then switch in and out a much lower impedance resistor divider like this:

^{simulate this circuit – Schematic created using CircuitLab}

Current only flows in the divider, or M2, when P?? is high. When P?? is low, that whole subsection is dormant.

Answer 3

The impedance of the voltage divider is way to high. If you can't lower the resistances then you should use an op-amp unity gain buffer with a rail-to-rail input and output.

Update:

The data sheet clearly indicates that the external resistance must be less than \$50k\Omega\$.

Table 51 (shown by OP) shows this as well.

With regard to the filter external capacitor, again the data sheet requires the total external capacitance be as small as possible:

Refer in particular to Note 2 of Figure 24 (reproduced below).

Quote: "A high \$C_{\text{parasitic}}\$ will downgrade conversion accuracy."

So the original answer still stands. The impedance is too high.
Now in addition, the capacitance is also too high.

Clearly the resistors were chosen to reduce current consumption. The capacitor is chosen for noise filtering.

If these are important then a buffer amplifier is required. There is a trade -off between of current draw between a lower impedance voltage divider and the quiescent current of the buffer amplifier.

Also from Note 2, the effect of high capacitance "... can be remedied by reducing \$f_{adc}\$". This is to increase the available sampling time based on the number of clock cycles.

Finally, notice the constant current source \$I_L\$. They aren't clear on what this is (leakage perhaps) but it will cause a voltage drop across the input resistance further introducing errors.

Answer 4

A sampling time of 13.5 cycles maybe is the problem try a longer sampling time that leads to a more accurate measurement. You need to try different sampling times to find the optimal accuracy.