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I am building a common source amplifier as shown below.
As you can see below, the Vsource signal is good sine, but after the capacitor the sine is totally canceled and I get only the DC bias.
I am supposed to see the sine with a DC offset after the C2 capacitor.
Where did I go wrong?
I am supposed to see the sinus with DC offset after the C2 capacitor. Where did I go wrong?
Short story: totally inappropriate values for C2 and L1. Longer story: -
I think the parallel inductor you use is for cancelling the gate-source capacitance of the MOSFET (parallel LC tank performs high impedance while resonating.)
This method requires that the MOSFET gate-source capacitance and inductor impedance are the same. For example, if the MOSFET input capacitance is 1nF (this big value usually appears in discrete power MOSFET,) its impedance is 1/(2pifC) = 15915ohm. For the inductor to reach this impedance at 10kHz, 2pifL = 15915ohm, the inductor should be 253.3mH, an unrealistic large inductance for signal application. In such low frequency circuit, a simple resistive divider biasing works well.
Your original 1nH inductor almost "shorts" your signal to ground (the "ground" is referred to a fixed voltage level.) Cacitor C2's 1pF impedance should be much smaller than input impedance. In your case, the 1pF capacitor (impedance = 16Mohm@10kHz) acts like an open circuit to the post-stage amplifier circuit.
If you are not sure how to choose DC blocking capacitor C2, the simplest way is by testing different values from small to big until the Vsource amplitude is approximately equal to the MOSFET side signal.
