2
\$\begingroup\$

As far as memory cells go (SRAM/ROM/Registers) in simple chips everything i've looked at seems to use the Two-Inverter CMOS schematic (Just from readings/googling and such).

In I guess "real life" chips are Registers/ROM/etc.. created using Inverters or something different (like an SR latch.....etc...)

That being said what kind of Latch/Flip Flop are most commonly used in Computer Architecture (Like a Counter or Adder or Shift Register)?

Since there are like 8-9 different types of Latches/Flip Flops all together (I've heard JK is most 'versatile' but that doesn't necessarily mean it's used the most)

\$\endgroup\$
3
\$\begingroup\$

It is possible to construct a RAM out of flip flops and multiplexers. Such designs require a lot of silicon, but they can be very fast. Further, such designs inherently allow a RAM to any number of read ports independent from its write port and allow predictable behavior if a memory location is written and read on the same cycle (the read is guaranteed to yield old data for the duration of the cycle).

One could also construct a RAM using using a pair of inverters with pass gates on the feedback path, so that while new data was being written the circuitry performing the right would not have to fight the RAM's feedback transistors. Doing such a design "properly" in CMOS would require eight transistors for each RAM cell--a considerable improvement over using a flip flop per cell. Unfortunately, it would also require having both active-high and active-low select lines for each row.

A common approach to constructing large static RAMs is to have a pair of inverters which unconditionally feed back to each other, but have the P-channel side be "weak" enough to be overpowered by a couple of N-channel transistors (one of which may be quite big) in series with the column bus wire. This will require two column wires--each tied to one inverter through an N-channel pass transistor--but both pass transistors may be driven by a common row wire. A memory cell is written by enabling it and grounding one of the column wires. The transistor driving that wire will initially have to fight the cell's P-channel transistor, but once it has been overpowered the other side's P-channel transistor will turn on and the P-channel transistor one was fighting will switch off. The "bus contention" state will thus only exist for a moment.

Of course, once one gets into larger memories it becomes common to ditch the static-RAM architecture in favor of dynamic RAM which not only reduces each memory cell to a single transistor, but does so with a layout that ends up being more compact than almost any other layout one could do with the same number of transistors.

| improve this answer | |
\$\endgroup\$
2
\$\begingroup\$

The "D" flip-flop is used almost exclusively; it's what most logic synthesis tools will create, and it's easy to understand and analyse in operation. Often it will have an asynchronous reset added, and all the reset pins will be wired together to the chip's reset pin.

Transparent (T) latches see some use in clock gating.

| improve this answer | |
\$\endgroup\$
  • \$\begingroup\$ Why do I see so much reference to JK Flip Flops when it comes to counters/adders/etc? Does this also go for Registers as well? or are most registers just made using inverters? \$\endgroup\$ – user3073 Apr 18 '13 at 15:27
  • \$\begingroup\$ Obsolete textbooks, or divergence between academic and commercial practice maybe? Most people doing design will write "reg [15:0] foo;" in Verilog and expect the toolchain to generate 16 DFFs for a register. Another aspect to consider is "design for test" (DFT) and the process of connecting flops together in a scan chain: effectively turning the entire chip into a very large shift register so that it can be tested. \$\endgroup\$ – pjc50 Apr 18 '13 at 16:02
  • \$\begingroup\$ I've usually heard term "T" associated with "Toggle" flip flops, which are used a lot in CPLDs in scenarios where an input should be loaded with a value when some complex combination of conditions applies. If for example one wants to have an input load from D0 when A0-A7 are all high, load from D1 when the address inputs are all low, and otherwise stay unchanged, a T latch would require using four product terms with a T latch, but a D latch would require using 58 (or else using an extra combinatorial macrocell). \$\endgroup\$ – supercat Apr 18 '13 at 16:18
1
\$\begingroup\$

Since memory cells need to be as small as possible, they are not constructed as flip flops but rather as cross-coupled inverters (often called a bi-stable latch) with pass elements to read/write data/databar into the cell, at least this is how SRAMs and registers are built.

| improve this answer | |
\$\endgroup\$
  • \$\begingroup\$ That makes sense. Side question, do you know how ROM is read from based on a grid like this? electronicproducts.com/images2/fabd_fun_nvram_1_oct2011.gif Since ROM is read only, are we just concerned with what the word line is outputting? \$\endgroup\$ – user3073 Apr 18 '13 at 15:44
  • \$\begingroup\$ In that image, "word line" is the input (one and only one is selected) and the "bit lines" are the output. \$\endgroup\$ – pjc50 Apr 18 '13 at 15:56
  • \$\begingroup\$ pjc50 is correct. The gif that you're pointing to shows a simple view used for illustrative purposes. A word line in a real memory is typically the signal that accesses an entire row of data bits. It is decoded from the address driven to the memory by the processor. If a row of data contains many bytes, the lower address bits define the column address and which byte in the row to access. \$\endgroup\$ – gman Apr 18 '13 at 21:07

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy