What can go wrong when producing an ASIC from an FPGA-verified verilog design?

Question

Given a Verilog design fully validated on an FPGA prototyping system, and someone who has never done an ASIC before, what are the chances that a service like CMP will ship fully usable chips on the first try? As far as I can tell, they provide the cell library and the tools, and do a DRC, so in theory it seems like just taking the RTL and compiling the design with their cell libraries should result in a usable chip.

What kind of things can go wrong when moving an FPGA-validated design onto a basic process like CMP's 0.35μm CMOS process?

If the design works on FPGA but not on the chip, is it debuggable without very specialized services like decapsulation and microprobing?

Answer 1

Lots ...

A FPGA verification is just a functional verification or something that you can use to emulate the final chip in system before you get the final Silicon.

There are companies that provide FPGA to Si conversions and they do it via different methods. Either they have a structure that maps 1:1 to the FPGA structure (really just a metal and routing change) Or they know how to get timing closure with std cells.

The linked to website is for Std cells, so unless you know what you're doing be prepared to get it wrong. The timing closure, the regressions and constraints used in FPGA synthesis is a subset of what you need to get a Std cell out the door. So you may have RTL, which certainly will change. The P&R will be driven by very different constraints than what a FPGA uses. You'll have to be more explicit and detailed in critical paths than you would in a FPGA.

The debuggablility is a factor of whether you have scan insertion, JTAG interfaces and built in debug support. If you think you can rely on a probe-station and advanced tools to probe inside the chip you've already lost the game. MOST signals are not available or are only available once the chip is greatly disabled. And some signals aren't even probable as the capacitance of the probe is too large.

You must design in test from the get go. Full stop. So the RTL now is no longer the same RTL you started out with.

Answer 2

It looks like CMP takes GDSII files, so it seems that the entire backend flow of RTL production is up to you to do.

To get a functioning chip, you would need to do (this is not a complete list, just off top of my head):

• Correctly performing the timing analysis of your circuit looking for setup and hold issues
• Doing some gate level verification on your design (poor RTL coding style can lead to issues where the simulation diverges from actual gate level operation, need to check for things like x-propagation)

If the design works on FPGA but not on the chip, is it debuggable without very specialized services like decapsulation and microprobing?

It's debuggable if you design your chip to be debug friendly. If your chip has one input and one output and the output fails, then you will have a very hard time. Typically professional designs would include things like test modes and scan chains (where you can serialize and scan out every register in your design through a jtag interface, as well as input a serial stream to initialize the registers in your design to a specific state). A lot of time investment is required to properly code a chip for good debug though, so you can decide if the time investment is worthwhile to you based on your chip's complexity.

Answer 3

See How is ASIC design different from FPGA HDL synthesis?

The layout and instantiation process is very different between the two; are you using one of the ASIC "hard copy" services, or resynthesising all of the logic?

You will have to do all the timing closure and layout yourself, and resimulate the final gate-level netlist. Assuming that works, you will also need to check your power consumption, including inrush current; you may get something that works but burns out the single bond wire you used for your power pin, or otherwise overheats and fails.

If you have any analog parts on your chip (regulators, clock PLLs) you will need to re-validate their use.

As the other answer says, you will want some sort of DFT arrangement; at the bare minimum you need enough scan to identify manufacturing defects.

Edit: it is very much worth hiring a "backend" firm to do this for you. It will cost you £10-£50k but save you at least that much in failed IC production.