I was looking at Garber files of the boost PFC reference designs by TI for my own SMPS. I noticed that most of their design don't make full use of the plane by filling them with a ground pour for example [image of PMP40766]: enter image description here

*top layer yellow and bottom layer blue.

All of their boost SMPS do not make use of full plane ground whilst most guidelines suggest filling void areas with ground pour, so why doesn't TI do so?

For my design I was thinking of making the bottom layer a full ground pour with all my components connected on the top layer, but seeing how TI places components in both layers it seems a waste to not use the bottom plane.

  • \$\begingroup\$ Also consider that it can be much easier to visualize where currents go physically without any planes visible. Could add Vcc and Vss as internal layer planes and "tap into" the supply at well-defined points with vias (like "star" ground for example.) Regardless, it is up to the implementer to think of all these things and design robustly. \$\endgroup\$
    – rdtsc
    Mar 30, 2023 at 19:54

3 Answers 3


Reference designs are not for general application, and don't need to meet safety or EMC standards. Safety is pretty self-evident as it's a bare board, but in particular notice the lack of EMC plots on this product.

That doesn't necessarily mean they've done a bad job. I was impressed with the response of the UCC25630-1EVM-291 I used last year. I don't know that it would pass regulations (assuming it's paired with a PFC, placed in an enclosure, and so on), but it wasn't troublesome for my probing at least (which puts a rough limit of around 100mV peak in the say 2 to 200MHz range, and probably even less given I hardly noticed it at all; regulations will want to see more like 10mV or below, depending on wave shape).

Regarding plane use or not, power supplies I would say are a looser sort of application for them.

It is certainly possible to implement designs without planes, as countless commercial units attest to -- many using only a single layer of copper (absolute minimal PCB cost!) where planes are completely impossible. While routing is very critical, it can also be very counterintuitive: both in respect of what's best in electrical terms, as well as what they can get away with despite that(!).

There is a very old rule of thumb in switching design, to minimize area of the switching loop. But, thanks to the excellent performance of multilayer planar designs, I have found time and time again that this is not only incorrect advice, but actively harmful.


My first and most notable illustration of this was the design of a 5kW inverter module, using MOSFETs at over 400kHz, which I dutifully laid out using a multilayer board, routing DC_P, DC_N and SW (the supply rails and switch node, per half-bridge section) as planes. The result was 80% voltage overshoot (a disaster using 900V MOSFETs from a 650V DC link; we had to use 1200V MOSFETs to continue development at this stage), and current spikes of around 80A per MOSFET (when hard switching at turn-on). I attempted to clamp the voltage overshoot with rectifiers; the dI/dt was so high, even with a fast (FRED) rectifier rated 30A, the peak forward voltage was 60V, less than half of which I could reasonably attribute to lead inductance alone.

I also discovered that, despite the average rectified current being minuscule (the pulse was ~100ns long, quite low duty cycle), even 12A rectifiers would fail after some seconds, never even getting warm -- I suspect perhaps an electromigration failure mode, due to the extreme peak current, or perhaps other failure modes due to the high transient forward voltage or uneven voltage across the die chip; who knows. The 30A rectifier was necessary to meet this [poorly- or un-defined] short-time surge current rating, despite the average current being so much smaller.

The characteristic frequency of the overshoot (ringing) corresponded exactly to the Coss of the transistors (in this case, about a nF), and the frequency suggested an inductance of merely 15nH between transistors. Surely I had done my due diligence, surely inductance can be no less than this? (This is basically the lead inductance of the SOT-227 MOSFET modules used. Multilead D2PAK and D3PAK, and DFN, packages are available now -- including extremely fast GaN semiconductors as well -- which offer much lower inductance, and integrating much better with a multilayer PCB. But this was about 12 years ago, before such packages were available, or at such power levels.)

After some analysis, and several revisions, I established that the loop inductance was too low for the application, and I intentionally increased it, to about 100nH. I did this by continuing to use the multilayer design, but I opened a loop between DC_P and DC_N nets -- a hole through the board, a blank region of no copper fill -- which given the loop area (and some other geometric factors that are hard to calculate so I'm sure I didn't get it quite exact) totaled about this inductance. This would only exacerbate the voltage overshoot at the transistors, but the catch is, now dI/dt is manageable -- I can use an ordinary size rectifier (12A or so) as part of a snubber circuit, and dump the inductive energy into a capacitor and resistor (voltage peak snubber) where it's eventually dissipated. And the stray inductance of the diode and capacitor do not spoil the whole deal, because again, dI/dt is much more modest. This resulted in a maximum power dissipation somewhere around 200 or 300W at no load (hard switching), dropping significantly under inductive load (as it enters ZVS), then going back up to 100-200W at full load (which was something like 20A RMS at 650V supply). Maximum voltage overshoot went down to 20% or so, making 900V transistors feasible (which was a big deal as SuperJunction technology hadn't quite filtered down to these products yet, either; the difference in Rds(on) between 900V and 1200V transistors was huge).

(To clarify on exact numbers here, I don't have notes handy from back then and I'm going by memory. I think the first boards had the ringing around 60MHz; the 1nF and 15nH figures quoted above would only come to 41MHz though. Coss was probably less than 1nH at ~600V, in which case the ~1nF figure I remember is probably more of an averaged value, since Coss is higher at low Vds. Which figure you pick -- instantaneous, or averaged or effective under various conditions (time-averaged, energy-averaged, etc.) -- depends on what you're doing.)

Another story: I was consulted to address emissions of a power supply module. The original design was worse than Swiss cheese: it was done entirely without planes, and traces were thin and routed everywhere, including making several loops in some nets (VAUX and DC_N). There was literally nothing I could tell about its EMC behavior: I could place 'Y' capacitors in strategic locations and control emissions below only about 10MHz, and that was it. It was an utter free-for-all above there. Craziest to me was, probing with an inductive loop, just, the entire space around the module -- in a sphere about a foot (0.3m) radius -- it was just a cacophony of emissions! There was absolutely nothing I could see or do; emissions showed up completely across the board, there was no way to measure anything, no way to apply snubbers or gate resistors for example. Even heroic efforts to cut and reroute traces were in vain.

I ripped up the layout, redid it with planes, improved placement a bit (original component placement wasn't too bad, as it happens), and made a couple minor changes to the circuit and components (most significant is probably using SiC schottky for the PFC rectifier; there are very few remaining applications for PN rectifiers anymore, it's quite impressive what they've done with schottky these days). The improved efficiency was nice, but most significantly, emissions dropped by over 20dB, and by moving around 'Y' capacitors, I found that emissions were controllable up to about 60MHz.

By "controllable", I mean that emissions do what I expect them to, in response to component changes, like connecting capacitors between planes or from planes to ground. (Using "Y capacitor" in the sense of: a capacitor, between a mains-referenced net (line, primary-side DC +/-, etc.), and ground, which is generally Y1 safety rated for this purpose.) We can draw an equivalent circuit for the common mode, which these capacitors control; this circuit remains applicable and useful up to the given cutoff frequency. So, the original "Swiss cheese" design was too complex to analyze in any reasonable way beyond 10MHz; the "planes" design remained workable in this way up to 60MHz. Given the ESL (lead length) of these capacitors, that's a pretty good showing and you'd have to work hard to go much further.

As for ground planes:

The most fundamental reason you want to use them, is shielding. High-frequency currents follow the path of traces over the plane. By merely spacing traces apart, over a plane, isolation is obtained. Isolation, means you can reason about one section of the circuit, without having to account for other parts. Analysis is tractable: the circuit's nodal analysis matrix is [near-]sparse. Whereas routing those traces through space, with a ground trace to return between them (or beside them, even multiple), the voltage drop along that ground trace (from each respective trace's current flow) is significant, and therefore so too the coupling between traces (as measured at either end, i.e. the voltage between trace and ground at the point of use).

Shielding is tricky at SMPS frequencies, though. PCB copper is thin: even 2 x 2oz. (as you might have on a high power board with inner VCC/GND planes) has only modest attenuation at 100kHz (~40dB?).

In more recent work, I've noticed some quirks using planes/pours. Large pours have significant capacitance. These can be excited by switching waveforms, even coupled through unexpected paths, like the stray capacitance of an inductor, or by minor aspects of switching waveforms, like the smooth ramp of a transistor's turn-off interrupted by the sudden stop of a clamp diode (or a MOSFET's suddenly high Coss). The latter isn't evident on the oscilloscope, because it's a fast twiddle of just a few volts, at the top of a 400V edge; but again, that's more than enough to be an EMC problem, if it couples out to wires, or gets radiated to fields, without enough attenuation.

For reference, effects in this range can be from switching edges in the 10ns range (typical for modern SJ MOSFETs), with resonant peaks over 100MHz (due to lead inductances ~10nH and pour/plane or junction capacitances ~100s pF). Transistors can also exhibit stray oscillation, particularly when a low G-S impedance appears at such frequencies; a common pitfall is a S-G clamp zener, the capacitance of which gives a series resonance (very low impedance) at 100s MHz. Modern MOSFETs can oscillate in this way at 400MHz or more! The oscillation doesn't have much amplitude (the available RF power drops precipitously beyond 20MHz or so; as fast as they are, they make surprisingly poor RF amplifiers!), but still more than enough to run into EMC problems.

Other plane quirks arise due to the limited space available in an SMPS design, and the outsized effect of transformers and inductors -- which are themselves large pieces of metal with high frequencies applied to them, so plane and wave and transmission line effects all play some role with them, too. (I mean this in contrast to more ordinary circuitry like digital logic and point-of-load converters (switching regulators), where components and current loops are small in relation to the plane that spans most/all of the board.) Probing a recent design, I notice a substantial amount of magnetic field from the power transformer "leaking" around edges of the ground plane -- where it can interfere with traces near the edge of the plane, or indeed the induced currents in the plane itself make for ground loop currents that would otherwise leave you scratching your head (it's not from currents flowing between components!). This has consequences for probing (especially low-level probing like control loop compensation, which was where I noticed it the most; the probe point was near the edge of the plane), as well as EMI.

I've also seen peculiar behavior of SuperJunction MOSFETs, even under seemingly very mild conditions (weak gate drive). I don't think this last one is cause for concern, but it goes to show how far we've come in MOSFET designs, that they are no longer reasonable to model as transconductance devices with gently varying dependent capacitors; they are much more nonlinear than that, and might be better modeled as switches with recovery, like PN diodes (ironically enough). (Emphasis on "like": they are still majority-carrier devices, and the "recovery" effect is still capacitive in nature. It does have some loss associated with it, however.)

All in all, I can't possibly begin to express over a decade of, to be fair, relatively meager experience, in a mere post here; or even in several books. On that note, do check out such classics as Henry Ott's Electromagnetic Compatibility Engineering, by the way!

Nor could you be expected to understand in less than, oh heck even some months of intensive study I think one would be hard pressed to figure it out, even between a very talented teacher and student; these skills are better honed over years of experience, and many don't learn them at all, whether by avoiding them, or lack of effort, or the sheer complexity of the subject -- as I say often, EMC is a holistic study, and depends on almost every element in the system.

On the upside, this does mean there's plenty of engineering to be done, out there, without having to learn EMC. An understanding definitely helps with power supply design, but there's also less demand for that -- units are available off-the-shelf for good reason! And, one can indeed approach PSU design in a haphazard, evolutionary manner, making small tweaks until the damn thing finally passes. All a matter of time and budget. Conversely, EMC experts are expensive, which is good for reducing time-to-market, but can easily eat into that budget as well.


There are at least two reasons:

First of all, you want to control the current path in a switching power supply. Because of the high frequencies and large currents, the instantaneous potential can be different by several volts when switching high currents due to inductance and resistance of the copper. So you want to partition your ground so that high currents are not flowing in the plane near your lower-power components.

Secondly, the wide traces required for high current signals form a capacitor when they are directly above the ground plane, which can couple transient voltages into the ground at the instant of switching.


A ground-pour on this 2-layer design would have too many gaps to be useful.

There two main benefits to a ground plane:

  1. Plane acts as a catch-all return path when there are too many current loops to analyze manually
  2. Plane acts as a shorted coil for any current loop, reducing their inductance and radiated emissions

and one main downside:

  1. Plane acts as a common conductor that spreads noise between PCB areas

With this 2-layer design both layers are already quite full. A ground fill would not provide a good ground plane, as it would have too many gaps. It would still provide a common conductor, spreading noise from high-voltage switching parts to low-voltage control parts.

If a continuous ground plane was desired, the PCB would have to be upgraded to a 4-layer design. It would likely reduce EMC emissions, though some care would be needed to avoid noise coupling within the PCB itself.

What has TI done to manage without a ground pour?

They have made careful analysis of the high-current paths. I have traced here the first half, up to C11. As you can see, the loops are about as small as possible. Purple is the input voltage up to C5, green is the boost path when Q1 is on and red is the boost path when Q1 is off.

Current paths in PCB image

Because there are only a few high-current paths, there is no need for a catch-all ground plane under them. But you will notice that under the control circuitry, there is a patch of ground fill.

  • \$\begingroup\$ Wouldn't it make sense to have all the high current paths to be on the same layer instead of having vias that will have to be relatively large to accommodate the high currents? \$\endgroup\$
    – KMN
    Mar 31, 2023 at 11:01
  • \$\begingroup\$ @KMN There are not many vias that I can see. Some of the traces are on both layers, and the layer switches happen at through-hole component legs. Near Q4 there is an array of 9 vias, presumably for current handling. \$\endgroup\$
    – jpa
    Mar 31, 2023 at 13:35

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