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I have a 4 layer PCB. The stackup is as follows:

SIG + PWR | GND | GND | SIG + PWR

Now I want to connect both GND planes with each other. EasyEDA Pro has this feature called "suture vias". If I add these vias get created. The picture with the newly created vias is below (highlighted are the "suture vias"). These vias start at the first GND layer and end in the second GND layer.

enter image description here

My question is, does it make sense that there are so few of them and has the position of them influence on the electric characteristics (impedance, inductance), or just the way current "flows".

This is the MAX6676 Part:

enter image description here

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    \$\begingroup\$ "These vias start at the first GND layer and end in the second GND layer." That's a blind via and will add cost to your PCB. Do you need them at all? How crowded is your design? How did you end up with that stackup? \$\endgroup\$
    – winny
    Commented Mar 31, 2023 at 12:58
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    \$\begingroup\$ General best practices are: add as many vias as possible, to improve impedance and EMI characteristics. Don't use blind vias but connect all 4 layers, unless your layout is extremely tight. The layout on the picture doesn't seem that extreme although it would be helpful to see the layers with actual traces. \$\endgroup\$
    – Lundin
    Commented Mar 31, 2023 at 13:19
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    \$\begingroup\$ My personal opinion is that you move 5 volts and 3.3 volts from the top and bottom layers to the 3rd layer and just use one GND plane on the 2nd layer. Also, I'd be keen to add test points on useful nodes in case you need to debug your design and use the holes for scope connections. \$\endgroup\$
    – Andy aka
    Commented Mar 31, 2023 at 13:32
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    \$\begingroup\$ You definitely should tie your grounds together. But the elephant in the room is that your are wasting a layer by having two GND layers next to each other and sacrificing your power planes. Do you really need both +5 and +3.3? Ideally, one solid 3.3 V plane. Second best, 5 and 3.3 V parts sectioned and a split 3.3/5 V plane. \$\endgroup\$
    – winny
    Commented Mar 31, 2023 at 13:34
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    \$\begingroup\$ JLCPCB doesn't offer blind vias at all, so if you're planning to use them (or any of the low cost vendors), you need to avoid them. \$\endgroup\$
    – user1850479
    Commented Mar 31, 2023 at 17:26

2 Answers 2

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If you are doing anything that is low speed (say lower than 10's of MHz) and not precision (like a few mV of ground bounce doesn't matter to ADC's), then it doesn't matter. Connect the grounds together everywhere.

If you are doing anything with transmission lines or RF then it would be best to tie the grounds together because the return currents need to travel back on ground.

If you have ADC's that are say 16bit and above then you need to pay attention to return currents on ground and noise from switching loads.

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  • \$\begingroup\$ On the top right I have a chip (MAX6675) which should have 0 ground bounce. How can I achieve this? How can I pay attention for return currents? \$\endgroup\$
    – Cem Pamir Bana
    Commented Mar 31, 2023 at 17:00
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    \$\begingroup\$ I wouldn't worry about that because the sensor is not grounded and the sensor and ADC are integrated into the MAX6675 which means they are going to be on the same ground. Just make sure you don't ground the signals to the thermocouple. It also has a vref built in so it should be quite noise immune. Keeping it on the corner is the best place for it. \$\endgroup\$
    – Voltage Spike ♦
    Commented Mar 31, 2023 at 17:04
  • \$\begingroup\$ I added a picture of the top right. The T- Pin is connected to GND aswell as the MAX6675. Should I somehow split the GND Plane below that so that it does not connect to the other GND Plane and is only connected through a small slit. Or dou you think it does not matter and I can neglect that all. \$\endgroup\$
    – Cem Pamir Bana
    Commented Mar 31, 2023 at 17:14
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    \$\begingroup\$ Actually, you do need to ground the thermocouple, I would do it like you are doing or put a trace on the top layer that you could cut if you wanted to modify it. \$\endgroup\$
    – Voltage Spike ♦
    Commented Mar 31, 2023 at 17:16
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Just to explain the observed function --

There are few of them, because it's a trivial algorithm that places them on the specified grid and offset, if that spot is clear of any obstructions. I'm not familiar with EasyEDA Pro but I'm guessing this is the function; surely there would be more placed if it were checking locations and adjusting to avoid collisions (placing off grid, if an opening can be found nearby), or placed differently if it detected existing GND vias and ranked positions by need (say prioritizing near traces/buses, or a diffusion dithering process to make via density more even).

You have about 50 other vias, intentionally placed, which serve the same function, and are generally spread about the board. I wouldn't worry about it.

I'm more concerned about the small vias in component pads, of which at least four are shown just in the tiny excerpt alone. I also see vias which must clear the yellow layer yet which do not exist in the larger screenshot. A tip: you will receive better help when your supporting information is clear and consistent; it appears these screenshots are from different stages of the design.

Oh, those are blind/buried vias, aren't they? The bi-color drill? Oh dear.

I already see comments mentioning the cost of blind/buried vias so I will not add much here at this time, but suffice it to say they add cost and complexity to the design, and based on what is presented so far, I see absolutely no justification for using them. Stub lengths are irrelevant until the highest of frequencies (multiple GHz), and only having GND for inner layers means you're needlessly hampering your own grounding ability by connecting to one layer preferentially.

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