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Somehow I’ve messed up my Altium settings and I cannot for the life of my work out what’s wrong!

I have routed various differential pairs earlier this week and when changing layers the vias were nicely spaced… as expected when I change layer the traces space out a bit so that the vias don’t collide.

But now, I’ve messed something up so that the vias are touching because the traces are not spacing out enough near the via and a short circuit violation is flagged….

What could it be?

Is it because I have the “maximum gap” set to the same as the minimum gap and preferred gap for the differential pair spacing?

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1 Answer 1

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Maybe your rule has changed, check HoleToHoleClearance under manufacturing in the desgin rules. Also make sure the query is correct

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  • \$\begingroup\$ Thank you I will check this and come back \$\endgroup\$ Commented Apr 1, 2023 at 9:06
  • \$\begingroup\$ I check and there is only 1 rule for hole spacing. It’s just a general rule… do I need a second rule to cover differential pair classes? \$\endgroup\$ Commented Apr 1, 2023 at 12:21
  • \$\begingroup\$ I tried to add a second rule for the differential class “DIFF85” but it didn’t do anything. (screenshot) I’m not sure if having all of the traces in an xSignals class as well is causing an issue? I added this second rule but it didn’t do anything. (screenshot) \$\endgroup\$ Commented Apr 1, 2023 at 12:24
  • \$\begingroup\$ If you already had a rule there and you have two rules, one had priority over the other \$\endgroup\$
    – Voltage Spike
    Commented Apr 1, 2023 at 14:52

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