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What I want is to implement a dual-channel memory architecture on a FPGA development board and verify that it is really faster than single channel.

At first I was thinking of configuring on-board DDR to dual-channel memory architecture, as long as a DDR chip is installed on the FPGA development board, say Digilent Arty A7 (Featuring Xilinx Artix-7 FPGA). But the answer to this question declined this possibility because hardware configuration is fixed and there is only one DDR3 chip on Arty A7 board. But I don't wanna give up. If external DDR is infeasible, how about internal DDR?

My understanding is that DDR memory is in essence a sequential digital logic circuit, nothing different from shift registers described in textbooks, only more complex. So, if I can do nothing about hardware configuration which is fixed on Arty A7, is there any chance to embed two DDR modules into the FPGA on Arty A7 board, because FPGA is designed to be programmable with regard to digital logic? I also heard that Micron provides Verilog IP core for each of its DDR memory models (e.g., here). In addition, I know Xilinx has MIG IP core for memory controller. So, I am thinking of putting two (or more) DDR IP cores into FPGA to satisfy the requirement of more than one DDR chips in dual-channel memory architecture, then putting two MIG memory controllers (or third-party memory controllers that support dual-channel operations), and designing some additional logic if necessary for controlling all of them to experiment dual-channel memory architecture totally within FPGA, without dependence on external multiple DDR chips and the same number of hardware memory controllers that support dual-channel architecture. If my idea if feasible, not only do I circumvent the hardware limit that Arty A7 board has only one DDR3 chip, I can also work on an FPGA board having no DDR chip at all like Digilent Basys 3 Artix-7 FPGA Developer Board, because everything can be emulated in FPGA. Capacity of DDR does not matter for me now.

Since I am new to this area, I posted this question here asking if my idea is feasible. If it is feasible, please say Yes, and let me know if there happens to be any reference Verilog code to implement a dual-channel memory architecture in FPGA. If not, please let me know what difficulty prevents implementation of it, like electrical signal voltage or timing I guess. Thanks a lot in advance for any professional advice that can guide a FPGA newbie who is eager to learn.

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  • \$\begingroup\$ @jsotola: If I can speak Chinese, I believe I can say it better. At least I'm trying to make myself understood and create a good communication. But some people who can speak English well are only trying to create division out of nothing, not only here in stackoverflow, but also in world relation between different countries. \$\endgroup\$
    – zzzhhh
    Commented Apr 1, 2023 at 23:05
  • \$\begingroup\$ I agree, it it always said better in your native language ... I did not realize that I was reading a translation ... my apologies to you ... \$\endgroup\$
    – jsotola
    Commented Apr 2, 2023 at 2:00
  • \$\begingroup\$ You can find some SDRAM verilog on opencores.org and probably other places. Anything free is probably not going to be very good, my opinion. A multi-channel memory controller is a difficult design, especially if you are looking to optimal performance. For that matter, a high performance single channel memory controller is complex, in particular if you plan to support multiple concurrent open banks. \$\endgroup\$
    – Troutdog
    Commented Apr 3, 2023 at 19:20

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The FPGA doesn't have any kind of DRAM memory in it at all. It has SRAM. If you want to simulate a DDR DRAM interface, sure, you can probably do that... but what's the point? You don't gain anything by connecting a DDR memory controller to a simulation of DDR memory that runs on SRAM. Why not just use the SRAM directly?

The simulation will have different timing than real DDR DRAM so it's probably not adequate for your experiment. You could design it to have exactly the same timing, but then you'd have to understand it in enough detail that you could probably simulate it on a computer without an FPGA.

Every 36-kilobit block of SRAM in the FPGA is its own channel, by the way. If you have the 35T version of the board you have 50 blocks (total 1.8 megabits) (7-series product selection guide) and the 100T version has 135 blocks (total 4.86 megabits, or about half a megabyte). As you can see, the FPGA doesn't have much memory built in which is why the board designers connected a separate memory chip to it, in case you need more memory.

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  • \$\begingroup\$ What's the point? Tell me first what's the point for first-year math students to do calculus exercises that have been solved by many many people again and again? What do math students gain by doing these exercises? Why don't they try to prove Goldbach's Conjecture in their first year? Only after a student master basic concept can s/he continue to do something that you think makes some sense. That's it. \$\endgroup\$
    – zzzhhh
    Commented Apr 1, 2023 at 23:16
  • \$\begingroup\$ @zzzhhh okay, but you're not really talking about an exercise here since DRAM memory interfaces are rather complicated and some important details are subtle. It's more of a final year project at least. What is the goal? To compare the speed of a CPU running a program, depending on the number of memory channels? You can run your desktop computer with for example 1x16GB stick versus 2x8GB. No need to build something from scratch for that. \$\endgroup\$ Commented Apr 2, 2023 at 10:22
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You can not use two DDR IP cores and connect then in parallel it just does not work that way. You get the performance the IP core gives you and that is it.

LPDDR4 has two channels per IC, but sometimes the IP core only supports single channel wenn accessing LPDDR4.

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