What I want is to implement a dual-channel memory architecture on a FPGA development board and verify that it is really faster than single channel.
At first I was thinking of configuring on-board DDR to dual-channel memory architecture, as long as a DDR chip is installed on the FPGA development board, say Digilent Arty A7 (Featuring Xilinx Artix-7 FPGA). But the answer to this question declined this possibility because hardware configuration is fixed and there is only one DDR3 chip on Arty A7 board. But I don't wanna give up. If external DDR is infeasible, how about internal DDR?
My understanding is that DDR memory is in essence a sequential digital logic circuit, nothing different from shift registers described in textbooks, only more complex. So, if I can do nothing about hardware configuration which is fixed on Arty A7, is there any chance to embed two DDR modules into the FPGA on Arty A7 board, because FPGA is designed to be programmable with regard to digital logic? I also heard that Micron provides Verilog IP core for each of its DDR memory models (e.g., here). In addition, I know Xilinx has MIG IP core for memory controller. So, I am thinking of putting two (or more) DDR IP cores into FPGA to satisfy the requirement of more than one DDR chips in dual-channel memory architecture, then putting two MIG memory controllers (or third-party memory controllers that support dual-channel operations), and designing some additional logic if necessary for controlling all of them to experiment dual-channel memory architecture totally within FPGA, without dependence on external multiple DDR chips and the same number of hardware memory controllers that support dual-channel architecture. If my idea if feasible, not only do I circumvent the hardware limit that Arty A7 board has only one DDR3 chip, I can also work on an FPGA board having no DDR chip at all like Digilent Basys 3 Artix-7 FPGA Developer Board, because everything can be emulated in FPGA. Capacity of DDR does not matter for me now.
Since I am new to this area, I posted this question here asking if my idea is feasible. If it is feasible, please say Yes, and let me know if there happens to be any reference Verilog code to implement a dual-channel memory architecture in FPGA. If not, please let me know what difficulty prevents implementation of it, like electrical signal voltage or timing I guess. Thanks a lot in advance for any professional advice that can guide a FPGA newbie who is eager to learn.