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I'm using Altium Designer to design a 4-layer PCB. In the power supply region (230 VAC power lines to an AC-DC converter), I'm routing exclusively on the bottom layer, and have added a rule to maintain a good amount of clearance around those high-voltage (HV) nets. This works fine for the polygon pour on the bottom layer, but the polygon pours on the remaining 3 layers are filled with copper that passes directly above the HV traces. The following image illustrates this:

Polygon pour HV clearance on bottom layer only

What I want to achieve is for the polygon pour clearance to extend to all 4 layers, but without adding traces to the remaining 3 layers. The following image illustrates what I want to do:

Polygon pour HV clearance extends on all 4 layers

I managed to do this by temporarily setting the HV traces as multi-layer, repouring and then resetting the HV traces to bottom layer only. The problem is that if I now repour again, all layers other than the bottom will again be filled with copper in the HV regions.

Is there a way to achieve the above effect in Altium Designer?

Edit — Some additional information

I can achieve what I want from an electrical perspective, by simply avoid pouring over the mains (HV) section altogether (using a Keep-Out region or drawing around it). The main reason I prefer to follow the "clearance across all layers" approach, as illustrated in the second image above, is because it maintains an even copper distribution across all layers, thus allowing for a better mechanical bonding and long-term stability of the 4 copper layers, 2 prepregs and dielectric in between (no large copper vertical gaps, especially at the edges of the PCB, where the mains section is usually located). I also find the "clearance across all layers" approach very elegant, in that it dynamically adapts to any placement/routing modifications that may happen in the future. I find it useful in general, and relatively simple to implement programmatically in Altium Designer, and was (still is) hoping for a simple solution, based on some clever use of rules in the PCB.

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2 Answers 2

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[ This is not an answer to the "How to do this in Altium? question.
Nevertheless, I'm compelled to post this. ]

The mains section (high voltage section) should be isolated from the secondary section laterally. Every polygon (trace, pad, plane, etc) on every layer under the high voltage section should belong to the high voltage section. Gap between the sections on every layer. Consult with standards as to how wide the gap needs to be (clearance and creepage). It's usually between 5mm and 8mm.

"Vertical isolation" between overlapping planes on different layers puts additional requirements on PCB fabrication. Designs with vertical isolation through a PCB are few.

Looking at the images in the question, I don't see reasons not to do isolation laterally. I don't see a reason to do isolation between overlapping planes on different layers.
My advice is to implement the isolation laterally.

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  • \$\begingroup\$ Thanks for that reply Nick. I could add a Keep Out region over the mains section and be done with it. I just wanted to balance the copper amount over the entire PCB (i.e., no missing copper on one side of the PCB), so that the PCB layers are mechanically bonded well, and at the same time there are no ground planes close to the HV traces (either laterally or across layers). My question still stands as long as there are copper pours on the mains section, even if they are isolated laterally, as there will still be copper over the HV traces, only separated by 0.07-0.12 mm of prepreg material. \$\endgroup\$
    – DrCeeVee
    Apr 2 at 1:35
  • \$\begingroup\$ Balanced PCB construction is a valid concern. Moderate differences in the layers are acceptable for balanced construction. Warping due to imbalance can occur when some layer in some region is 90% copper, but it's symmetrical counterpart is only 10% copper. The first set of layers in the O.P. already gives you balanced PCB construction. (I'm assuming that you'll add a gap.) Both top and bottom layers are all copper. Both inner layers are all copper. \$\endgroup\$
    – Nick Alexeev
    Apr 2 at 1:46
  • \$\begingroup\$ Another way to achieve balanced construction is to remove planes and copper pours in the main section altogether. Only traces remain. I see this in off-line AC-DC converters often. \$\endgroup\$
    – Nick Alexeev
    Apr 2 at 1:50
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No: clearance is not computed between layers, except specific combinations thereof (e.g. multilayer or keep-out*, to any single layer; silkscreen to soldermask; soldermask to copper; etc.).

*As of AD18 or so, keep-out is preferably handled by object property rather than using a dedicated layer, so this is more of a historical note (or for those still using older versions).

As others have commented/answered, the question being asked is most likely incorrect: AC mains is hazardous and prone to transients (up to 2.5kV, or more depending on standard). Secondary-side ground should not be anywhere near mains conductors, with a minimum around 4mm (how much again depends on the standard, as well as environment, and materials used).

The trivial solution is also the best solution: simply don't pour ground over/around these traces. It does not offer any apparent electrical, thermal or mechanical improvement, and severely compromises safety of the design.

AC_N should also be moved to clear further away from J2.

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  • \$\begingroup\$ Thanks for your reply Tim. You're certainly right about keeping the mains conductors well away from secondary elements. I was more concerned about keeping an even spread of copper over the entire PCB for mechanical reasons (bonding of the 4 layers + 2 prepregs + dielectric). I will most probably just not pour over the mains section traces, as you're suggesting. My question still stands, however, as what I'm proposing could be of some use in certain cases. I was hoping that this could be achieved via a special rule, to extend the clearance of certain traces across all PCB layers. \$\endgroup\$
    – DrCeeVee
    Apr 2 at 1:52
  • \$\begingroup\$ The most common substitute is using a polygon cutout, which can be made in the footprint (if you wish to customize it), or union'd with a component to keep them together while adjusting placement. But this does not scale automatically with design rules or number of layers. Copper balance is a differential (between top/bottom, mid1/mid2, etc.) problem, so does not affect the above solution. Also the region shown is entirely THT so warpage is most likely irrelevant. \$\endgroup\$
    – Tim Williams
    Apr 2 at 2:46
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    \$\begingroup\$ In the future, please avoid asking questions about a particular solution -- or about just that solution. When there is an underlying motivation or question or problem, please mention that as well, so that better overall solutions can be provided. This is called an "X-Y problem". In this case, the problem 'X' was "is copper balance a problem?", and the question about proposed solution 'Y' was "how to make copper pour evenly on all layers?" \$\endgroup\$
    – Tim Williams
    Apr 2 at 2:48
  • \$\begingroup\$ Thanks again Tim, for the comments, much appreciated. I will try to figure out an elegant way to do it, that dynamically adapts to changes in placement/routing. You've given me some ideas to try. As you recommended, I have already included some additional information in my original post, about my motivation for using the "clearance across all layers" approach. \$\endgroup\$
    – DrCeeVee
    Apr 2 at 6:17

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