From the results given by power analyzer, I find that the Xilinx FPGAs always have a high static power consumption no matter what your design is, although it will vary if your design utilize different number of resources.

What are the components consuming the static power on Xilinx FPGA reported by power analyzer?

My guess is: interconnect (wires and switches) + slice used + IOB used + memory used + ASIC component used (multiplier, adder, etc)


First, it depends on the family. Older ones have less leakage.

Interconnect does have a lot of transistors, so it is likely high.

Slices used is high (for the logic) and low (the configuration logic is optimized for power since it doesn't need speed).

IOB is low.

Memory and ASIC components I can't comment on.

  • \$\begingroup\$ My impression is that newer ones also have less leakage (per LUT or similar) :) I think from Xilinx's 6 series to 7 series they tried really hard to reduce the static power... V5 was a peak, V6 started the downward trend. But of course the devices keep getting denser, so it might not look downward from a whole-device point of view! \$\endgroup\$ – Martin Thompson Apr 19 '13 at 8:36

Any transistors in the FPGA that have power applied to them will consume static power, due to leakage through the transistor. Wires do not consume static power.

If you have a small design I guess that certain blocks would be power gated, which will reduce static power, but for anything that's used it will consume static power, which will increase linearly with the amount of 'stuff' used, mostly regardless of what it's used for.

  • \$\begingroup\$ Thank you for pointing out wires does not consume power. I find Brian's answer more detail. But your answer is also very good. \$\endgroup\$ – drdot Apr 23 '13 at 0:17

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