# Multisim simulation of a current division

I'm currently trying to simulate a current division for three transmission lines that are in parallel (but all of different lengths). I want to study how the current divide itself as we progressively increase the frequency from our power source. In order to do this, I'm trying to use Multisim. I've little experience in Multisim, but I know the bare basics.

Here's what my "code" looks like at the moment:

This is just a rough sketch but what confuses me is as to why the transmission line has four ports, wouldn't it be enough with just two? I'd be glad if someone could explain why this is the case so I can help finish my code and start simulating.

EDIT:

So I've tried learning more about transmission lines in Multisim and here's what my result looks like:

I used the specifications of a RG58 for the cables respectively, and choose the lengths as can be shown. However the result seems weird. At low frequencies, shouldn't all currents match up if this was done in for instance a lab? I've many questions regarding on how one can derive some sort of analytical expression for the current division of say $$\n\$$ transmission lines in parallel for some distinct lengths $$\l_j\$$, is there anyone who could provide information for how to solve such a problem so that I can then verify it in Multisim?

• I don't know Multisim, but every transmission line needs both a signal path and a current return path and potential reference. Presumably the other ports are there to allow you to connect the return and reference potential (physically, the ground plane that your transmission line is referenced to) Commented Apr 2, 2023 at 16:47
• It's surprising that the symbol appears symmetric, with no distinction between the signal ports and the reference ports. Are you sure you haven't chosen a symbol for a differential transmission line? Commented Apr 2, 2023 at 16:48
• @ThePhoton Yes, I now realized what the other ports have to be. Other than that, I couldn't find something that wasn't symmetric. I edited my answer, maybe you can help me out with the more "mathematical" part, so to speak. Commented Apr 3, 2023 at 13:36

SPICE transmission lines are an idealization, as many simulation elements are. Specifically, the ports are ideal, i.e. the common-mode current is zero / CM impedance is infinite. Therefore it does not matter whether it's coax, twisted pair, ferrite-loaded or what: you can add the shield current or common mode however you like, external to the TL element (which is just a delay).

While you would assume the TL components are simply straight wires through, consider that a real wire has common-mode impedance, which stacks up over time: the transient impedance (i.e. the impedance seen by a single wave front at the speed of light) might be low 100s Ω, and over repeated delays (electrical lengths) of that line, waves reflect back and forth, and current builds up. Eventually at DC, the waves decay, leaving current flow due to wire resistance and nothing else. The ideal TL however has infinite CM impedance, so this build-up does not happen, and the DC current flow is zero. It's simply an open circuit.

Put another way: the ideal TL includes an ideal transformer.

Put still another way: the ports are ideal ports, i.e. current into one pin flows exactly out the other pin; a port is a 2-terminal component, with some V-I characteristic (or more specifically, $$\v(t), i(t)\$$) and no immediate relation to other nodes in the circuit (except by definition of whatever network the ports represent -- in this case, a transmission line).

Note we could also have ports where there is one signal pin (of which the voltage and current are relevant), but common mode has been shorted instead of opened, i.e. everything is common ground. This is the more common case in RF circuitry, as we can make something reasonably common-ground with the use of ground planes and shielded enclosures. (Or, more precisely, the ground might still not be very common -- there may be some CM voltage, but we can make cables, connectors, etc. well enough shielded that CM and DM are well isolated and so can be treated separately; CM doesn't go away -- it's always and necessarily there, we can just approximate it away.)

In the second circuit, with the return paths grounded, the ports carry current, and the result is as expected.

As for the LF discrepancy, note two things:

1. You're using quite low impedance cables here. Zo is not the DC resistance, but the (AC) characteristic impedance. Typically this would be 50Ω. 0.14Ω is an extremely low impedance for a TL! Note, at least for the lossless TL case obviously, you have no way to input DC resistance, or AC loss (attenuation at frequency) or dispersion or whatever, so there is nothing to ensure current sharing between these, at DC at least.

2. You've committed a sin: inductors in parallel, or capacitors in series, give a degenerate case where the current in that loop, or the voltage on the node, is undefined (at DC). That is, the simulator could pick any initial value and be equally correct. But it will not try to, and instead emits a singular matrix error. (This also applies to voltage sources in parallel, and current sources in series.) Some series or shunt resistance must be provided to make the matrix well-conditioned again.

The steady-state impedance of a TL is given by the $$\\sinh\$$, $$\\tanh\$$, etc. of its electrical angle. These give zero at DC, and proportional (one end shorted) or inverse (one end open) with frequency for F ≪ Fo, that is to say, an inductor or capacitor respectively.

It seems it's managed to simulate regardless, and chosen somewhat arbitrary values in the process. I don't know offhand if this is a quirk of how TLs are handled, or if GMIN or RSHUNT or other settings affect this. You will most likely get correct DC values with individual resistors in series with the TLs, even small ones (try 1uΩ).