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According to here, the PCI Express TLP (Transaction Layer Packet) can target 4 different address spaces.

enter image description here

My question is about the IO and memory address spaces.

As we know, the PCI specification was first developed by Intel. And Intel's x86 processor has 2 major address spaces: IO and memory. I think that's why the PCI Express transactions can target 2 kinds of locations in system IO map and system memory map. Is it some kind of x86-specific lineage?

But how about ARM-based system? AFAIK there's no IO address space for ARM processors.

Does that mean the PCI Express IO address space is meaningless for ARM-based system?

Thanks.

ADD 1 --- 9:18 2023/4/19

A related thread: https://stackoverflow.com/questions/75265993/is-pci-cf8h-cfch-io-port-addresses-only-applicable-to-processors-with-an-io-ad

Some quote:

The method for generating configuration cycles is host dependent. In IA machines, special I/O ports are used. On other platforms, the PCI configuration space can be memory-mapped to certain address locations corresponding to the PCI host bridge in the host address domain.

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2 Answers 2

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But how about ARM-based system? AFAIK there's no IO address space for ARM processors.

ARM-based systems that fully support PCI spec still support I/O transfers. The I/O space is then mapped into memory somewhere.

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    \$\begingroup\$ I haven't looked at the implementation, but the ARM Firmware Suite Reference Guide does have functions such as uHALr_PCIIORead32 to access I/O space. \$\endgroup\$ Apr 3, 2023 at 17:29
  • \$\begingroup\$ This is exactly what I was thinking. I will elaborate about it later. \$\endgroup\$ Apr 4, 2023 at 8:22
  • \$\begingroup\$ @ChesterGillon Yep, IIRC these are the requisite memory-mapped accesses wrapped in an interface that clearly indicates the intent. \$\endgroup\$ Apr 4, 2023 at 16:48
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Yes. The I/O address space support is included for x86, and ARM does not even have instructions to access such a separate address space.

Even in the x86 world, the I/O space was never extended beyond the 16-bit limit, and almost all PCIe "I/O" ranges are memory mapped. The only PCIe devices that support the I/O space do so because they need to be compatible with old x86 devices such as (non-USB) serial/parallel port or VGA.

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