I am designing a fairly simple PCB with 4 layers and some IC-s.

The layers are:

  1. Top: Components + signals
  2. In1: GND
  3. In2: +3.3V
  4. Bot: Some signals

There is an IC with a lot of GND pins, and currently I did this: enter image description here

But I could just pour a GND plane also on the top plane and add some vias to connect the top GND to the inner layer.

What is the optimal solution here? Is my first solution valid / correct?

  • \$\begingroup\$ What are the signals? What you're asking about is the impedance of the PCB, to the component in question, and between connected components. Even a "fairly simple" design can be quite involved if these quantities must be very low, or to tight tolerances! \$\endgroup\$ Apr 3, 2023 at 20:51
  • \$\begingroup\$ Signals are SPI traces running on the top layer \$\endgroup\$
    – Gabi
    Apr 3, 2023 at 21:16
  • \$\begingroup\$ @Gabi How fast is the SPI ? For context, what's the purpose of the entire device? \$\endgroup\$ Apr 4, 2023 at 2:13
  • \$\begingroup\$ This is a accelerometer + gyroscope IC from murata: murata.com/en-global/products/sensor/gyro/overview/lineup/… SPI speed is max 10 Mhz, but I would only use it at lower freqs like 2 Mhz. \$\endgroup\$
    – Gabi
    Apr 4, 2023 at 6:53

1 Answer 1


There's no optimal solution but it's practical to use top and bottom layers for signal, one inner layer for GND, and the remaining one for power. Especially if you have controlled impedances (e.g. 100-Ohm differential lines) it's better to keep these lines on the layer that GND comes next to.

Your approach seems fine. But, as a suggestion, you don't have to use a via for every single GND pin of the IC. You can short the adjacent ones (e.g. 31 and 32) and use a single via for them. Same for 28-29, and 24-26 (these can be shorted with a track behind p-25).


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