For powering Artix 7 FPGA I need power sequencing. In the Artix-7 data sheet it states that the recommended power-on sequence is VCCINT (1.0 V), VCCBRAM (1.0 V), VCCAUX (1.8 V), and VCCO (3.3 V). Therefore the sequence is 1.0 V, 1.8 V, and 3.3 V.

3.6 V and 1.0 V is regulated by 2 switching regulators from 12V input. Regulated 3.6 V will be used to generate 3.3 V and 1.8 V by 2 LDO regulators as in the schematic.

Can I directly connect the power good pin of the LD3920 (U23 component) to the enable pin MIC5301 (U25 component)? What is the correct way of doing this connection?

LD3920 Datasheet

MIC5301 Datasheet



1 Answer 1


Often yes. In this case its a little trickier.

Its quite normal to feed either power good or a divided down version of the output voltage into an enable. This works particularly well when the regulator being enabled has a "precision enable", which is essentially just a comparator with a fixed threshold, allowing the next regulator to turn on once the first regulator reaches a precise output voltage.

In the case of your circuit, there are two factors which mean that this won't work without a few more modifications.

Firstly, PG is actually an open drain output (its not obvious in the datasheet but "When the output voltage is higher than 0.92 * VOUT(nom), the PG pin goes to high impedance" Section 6.4) so at the very least it needs a pullup resistor to something (probably 3V6).

The second issue is that the MIC5301 defines the EN threshold as less than 0.2V for OFF, and greater than 1V for on.

Enable Input Voltage specification from MIC5301 datasheet

The open drain output of the LD39200 on the other hand can only pull the voltage as low as 0.4V worst case. This means that the LD39200 cannot guarantee pulling the voltage low enough to definitely keep the MIC5301 off. In other words, the logic is in the undefined window, and may produce unexpected behaviour.

LD39200 PG Open Drain Voltage Specification

I think because the EN threshold is quite wide for the MIC5301, your best bet might be to have a buffer sitting between PG and MIC5301, allowing you to properly drive defined logics levels (something like this). If you do, don't forget the open drain pullup on the LD39200 side, and I would also add a pulldown on the MIC5301 EN side too.

  • \$\begingroup\$ Thank you. Is going "high impedance" meaning it is floating so a pull up resistor needs to make it high voltage. Did i understand it correctly? Also since i will not drive the second regulator off only sequencing is needed when the circuit is powered, can i ignore second part of the solution. One example design uses just a pull up resistor. \$\endgroup\$
    – Cenk
    Apr 5, 2023 at 8:19
  • \$\begingroup\$ Yes - High Impedance does mean that the output is floating so needs a pull up resistor. Unfortunately, you can't really ignore the mismatch in logic levels. Sequencing is just another word for forcing a regulator to stay off until you are ready to switch it on. The LD39200 will try to pull the Enable line for the MIC5301 low, but it can't pull it down low enough to guarantee that the MIC5301 will be OFF until you want it to. \$\endgroup\$
    – Graham
    Apr 5, 2023 at 19:00
  • \$\begingroup\$ Hi Graham thank you for your answers. I will use the buffer like you suggested. To be sure: When there is a buffer between 2 regulators' power good and enable, i should use a pull up resistor at the PG side and a pull down resistor at the EN side. Is this what you suggest am i right? \$\endgroup\$
    – Cenk
    Apr 8, 2023 at 10:49

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