Basically my question is regarding maximum length of SPI routing, and route efficiently in my scenario and any timing issues(Setup and Hold).

I am just explaining my scenario. Please bear with me, it is very big message...

I have an EVK which has SPI exposed to a 10-pin connector, and I have slave board (RF board) which has SPI exposed to 20-pin connector.they can't be directly connected, that's why I am designing a 10-pin to 20-pin interfacing board to interface effectively.

Unfortunately because of mechanical constraints, i need to use a flex cable to route between 10-pin Connector on EVK to 20-pin interfacing board. Slave board directly mates to 20-pin connector of interfacing board.

I am running SPI at max 8Mhz with 4-20nS Rise times.

I don't have any control on Slave board and EVK side. Only i have control on 10-pin to 20-pin interfacing board.

I want to know what is the maximum length of flex cable can used between EVK and interfacing board.

What things can be done to mitigate SI problems and ensure signal quality. Is there any free tool (I have altium using which i am not able to simulate) to simulate this scenario. Is there any timing issues that need to be taken care of here.*

I want more of a quantitative explanation.


4-20ns rise time is pretty slow - each nanosecond is about 15cm at PCB trace speeds. Various rules of thumb exist - Howard Johnson proposes that if the length of your interconnect is < 1/6 of the risetime, you can treat it as a lumped circuit and neglect most of the signal integrity problems that rear their heads in longer circuits.

For you, 4ns is 60cm, so if your wires are shorter than 10cm, don't worry about it.

Regarding mitigations, without access to a simulator, the easy things to do are:

  • Series terminate the serial-clock line, some value between 27 and 47 ohms is usual.
  • Ensure that there is a ground return next to each signalling wire in the ribbon/flex cable. If you can't do that, ensure that the clock line is at least next to a ground line.
  • \$\begingroup\$ Good advise - for terminating (if required) i've got away with a terminator in series with 100pF so that dc levels aren't killed by the resistor being directly connected across the line to 0V. I might even raise this as a question because I'm interested in what the great and good would say on this site to this method which basically is: you only need to terminate for the really high frequency stuff in the data signals and clock signals. \$\endgroup\$ – Andy aka Apr 19 '13 at 14:00
  • \$\begingroup\$ That sounds like a parallel terminator. For a point-to-point clock, a series terminator at the source is usually a better choice (less power dissipation for one thing) \$\endgroup\$ – Martin Thompson Apr 23 '13 at 8:45

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