# How to measure the stability of a buck converter using LTspice

Below is my buck converter circuit. How can I check its stability using LTspice?

I need to measure GM and PM.

Is this true that a 30–60 degrees phase margin and a gain margin of 2–10 dB are desirable in a closed-loop system design?

As Jonathan suggested I connected a current source at the output.Please see my circuit diagram below.

May I know my current source spec is fine or not.

The output waveform obtained is given below.

The percentage overshoot is given by ( (4.2-3.3)/3.3)*100 = 27% .

This will give a PM of almost 40Deg.

Please correct me if I am wrong.

As Tobalt suggested,changed the current source spec.Please see below.

The output obtained is given below.My question is for finding the overshoot which portion I need to consider .The red one or Blue one.

Voltage across C2 and output voltage

Voltage across capacitor C2

• The way the output voltage of the converter heads down to zero in a straight line makes it appear as if the converter just shuts down entirely (constant-current capacitor discharge) - potentially because of a lack of bootstrap voltage. Could you check the voltage across C2 in your simulation? (And, as tobalt mentioned, try 10mA instead of 0A as the initial current of the current sink). The phase margin of the converter is fine. Apr 7 at 13:28
• @JonathanS,updated the question .please see the last image which contains Voltage at boost pin and output voltage
– Hari
Apr 9 at 12:48
• The important thing is not the voltage at the boost pin, but across C2. (In other words, the voltage difference between Boost and SW.) Could you plot this, please? Apr 9 at 13:45
• Added the new plot which contains voltage across the capacitor.Could you please check
– Hari
Apr 9 at 15:26
• Thanks for plotting that voltage. I'm really not sure what's going on with the converter during that time, though... It shouldn't drop down to zero like that, especially when it has sufficient bootstrap voltage, yet it somehow does. Apr 9 at 18:54

To get a rough estimate of the phase margin using a transient simulation, you can "whack" the output of the buck converter with a very fast load step, i.e. going from 0A to 1A within 1µs (and vice-versa). The amount of ringing you observe at the output is directly correlated to the phase margin. It'll be worst without a load resistor connected to the buck converter.

If the converter regains regulation without exhibiting any ringing after this load step, it's stable and has a phase margin of 50° or more. Check out this answer for a graph showing exemplary step responses for different phase margins. I've found that this method of determining the stability of switching converters in LTSpice is sufficient for most of my designs.

To get the phase and gain margins directly, you could build a linear AC equivalent of the LT1765 and the surrounding circuitry (replacing the PWM output stage with a voltage buffer of appropriate gain) and then perform an AC simulation. Alternatively, you could use a new tool that got introduced in LTSpice 17.1 and allows you to analyze the frequency response of switch-mode power supplies using a transient analysis. I wasn't aware of this yet; thanks to emnha for pointing this out in the comments.

Regarding your second question, I'd be a little nervous about a system that has less than 10dB gain margin. 10dB is the absolute minimum I aim for, and even that means that the system might become unstable if its gain changes by more than a factor of 3. Additionally, 30° phase margin will cause significant ringing as seen in the answer I linked above; I wouldn't go below 45°.

• Would this work? Apr 6 at 19:36
• @Jonathan , I edited the question with the methods suggested by you.If you don't mind could you please check
– Hari
Apr 7 at 6:19
• @emnha Wow nice new feature. If you want to add an answer to here electronics.stackexchange.com/q/652977/237061 I would gladly accept it. Apr 7 at 8:43
• @tobalt Sounds like you might've missed my comment I put on that question back when you asked it. Apr 7 at 17:31

About your load current model: The current load pulse should come only once the output voltage is equilibrated. I.e. put a delay of 100u. Also put a period like 10, not sure it works without this. Best put on-time to 100u, too, so you see both steps (behavior will differ).

The red but shows that your output regulation fails at 0 A load. The deep excursion down to almost 0 V shows a serious regulation issue. Maybe you can relax the pulse a bit by setting the off-phase current to an expectable minimum current like 10 mA or something ?

• @ tobalt,Changed the current source spec as per your suggestion and I updated the question.Could you please check the last portion
– Hari
Apr 7 at 9:56
• @Hari updated.. Apr 7 at 12:06