# Regarding the Static Full Adder Circuit

As per the book on Digital Integrated Circuits by Rabaey Et al. in the static CMOS implementation of Full adder circuit with Co= carry out and S= Sum As mentioned in the marked point of the attached image, the intrinsic load capacitance of the Co signal is 2 diffusion and 6 gate capacitances, plus the wiring capacitance.

• Can anyone please explain how are these 2 diffusion and 6 gate capacitance are occuring?
• What are the transistor sizes for this circuit?

The claim the circuit is slow contains a mention of ripple-carry adder:

• it is assumed that $$\C_o\$$ is routed to $$\C_i\$$ of exactly one identical adder.
I think it easy to count six gates labelled $$\C_i\$$.
• lamenting the capacitive load on $$\C_o\$$ suggests to make the transistors driving it wider.

Figure 11-4 doesn't literally implement $$\C_o = AB + BC_i + AC_i\$$, but an odd mix of
$$\C_o = (A + B)C_i + AB\$$ (N, pull-down) and $$\C_o = (A + B)(AB + C_i)\$$ (P, pull-up)

You can reduce the number of gates driven by $$\C_i\$$ by one or two duplicating one or both of the "internal $$\\neg C_o\$$ transistors".

one

• (I fail to see 2 diffusion capacitances - yet.) (Going to try and reduce #gate on $C_i$.) Apr 7 at 6:11
• The diffusion cap is the inverter driving Co. Yeah, I would not consider this load per se, but on the other hand, it's capacitive, and if it were a complex gate with a single device trying to swing a heavily-dotted output, then it does matter. Like the complex gates shown here tend to have the parallel devices pushed away from the output towards the supplies to reduce "load" on X and S-bar. May 16 at 2:09