As per the book on Digital Integrated Circuits by Rabaey Et al. in the static CMOS implementation of Full adder circuit with Co= carry out and S= Sum
As mentioned in the marked point of the attached image, the intrinsic load capacitance of the Co signal is 2 diffusion and 6 gate capacitances, plus the wiring capacitance.
- Can anyone please explain how are these 2 diffusion and 6 gate capacitance are occuring?
- What are the transistor sizes for this circuit?