0
\$\begingroup\$

I am constructing an electronic circuit that requires a power meter with a voltage signal output that represents the changes in power in a resistive load. It is crucial that the phase of this signal is correct, as the goal is to compare the phase of this signal with the phase of a reference signal further in the circuit (I will spare you the details, but this operation must remain unchanged).

The concept is as follows:

Obtain a voltage signal that represents the value of the current in the load (this part is relatively simple, see the implementation below), compare this signal with a triangular signal using an op-amp to obtain a square signal whose duty cycle represents the value of the current.

Use this square signal to control a switch, the input of which is a signal with a voltage that matches the voltage across the load.

Use a low-pass filter op-amp to calculate the average of the signal coming out of the switch, based on the fact that [value of the average = duty_cycle * amplitude of the input signal].

The basic principle cannot be changed; my question is about how to best implement this idea, not about using a different system.

For the comparison between the current signal and the triangular signal, the duty cycle (between 0 and 1) directly represents the value of the current only if the triangular signal itself oscillates between 0 and 1V (if smaller or larger, a multiplicative and dividing factor is involved). In my circuit, the currents are on the order of a few mA, and variations of this order are barely (if at all) perceived by the comparator. Therefore, I use a resistive divider to obtain a triangular signal with a lower amplitude.

My issue is the following: despite using a fairly responsive filter, I observe differences in behavior between the phase of the theoretical power signal and that of the signal generated by my circuit. Although the amplitude itself is not very important, I am concerned that it might also deteriorate the phase information (which is crucial).

Here is the current circuit: enter image description here

As well as the main signals (current, voltage, theoretical power, power signal), the fluctuations in the current and voltage values come from the overall circuit (it is not important how, I simply provide the graphs to show the difference between theoretical and measured power): enter image description here

As you can see, at some point the generated power signal decreases, and I don't know why. The phase is still accurate, but I worry that it might not always be the case (could it even induce phase errors in other cases?).

What are your thoughts on this? Do you have any suggestions on how to improve my circuit?

\$\endgroup\$
3
  • \$\begingroup\$ Is there any reason you can't just use an ordinary A/D converter, perhaps with a microcontroller where you can take multiple samples and perform the multiplication and other signal processing as required to compute instantaneous as well as true RMS voltage and power? \$\endgroup\$
    – PStechPaul
    Apr 8, 2023 at 1:50
  • \$\begingroup\$ A few things, why are your Current and Tension input values drifting? The LT1011 has good input offset spec's but you are comparing signals in the mv range so any offsets become significant in relation to the signals. The datasheet recommends that the Balance pins (5 & 6) not be left open, per page 7 they "can be used to adjust the input voltage offset or to add hysteresis. If offset balancing or hysteresis is not used, the BALANCE pins should be connected together with a 0.1μF capacitor." Maybe consider balancing. analog.com/media/en/technical-documentation/data-sheets/… \$\endgroup\$
    – Nedd
    Apr 8, 2023 at 1:52
  • \$\begingroup\$ It looks like the signals have a bandwidth of a few hundred hertz, so sampling at 1 mSec to 100 us should be sufficient and well within capability of a PIC or AVR device. \$\endgroup\$
    – PStechPaul
    Apr 8, 2023 at 1:56

0

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service and acknowledge you have read our privacy policy.