I'm trying to add two numbers together, and it's giving an odd result.

Here's the code,

`timescale 1ns / 1ps

module addition_test(
input clk,
output reg [31:0] probe_00, probe_01

reg [31:0] a, b;
reg sel;

always @(posedge clk)begin


        1'b0 : begin

            a <= 15;
            b <= 5;
            sel <= 1'b1;


        1'b1 : begin

            probe_00 <= {a[1:0],a[31:2]}^{a[12:0],a[31:13]}^{a[21:0],a[31:22]};
            probe_01 <= {a[1:0],a[31:2]}^{a[12:0],a[31:13]}^{a[21:0],a[31:22]} + b;


        default : begin

            sel <= 1'b0;





probe_00 evaluates to C0783C03 as expected, but probe_01 evaluates to C0783C06, which is off by 2. I expect probe_01 to be C0783C08.

I've tried simulating this with both Vivado and iverilog, and tried both blocking and nonblocking assignments, and I still get the same result.

Can anyone tell me what I'm doing wrong here?

probe_00 = a[1:0],a[31:2]}^{a[12:0],a[31:13]}^{a[21:0],a[31:22]};
probe_01 = {a[1:0],a[31:2]}^{a[12:0],a[31:13]}^{a[21:0],a[31:22]} + b;

gives: 00000000000000000000000000000101. That is the entirety of my code, except for my testbench, which only inputs the clock and takes the output from addition_test().

  • \$\begingroup\$ Hope b did not change elsewhere in your code. Can you print the value of b using $display just at the point where the addition is happening? \$\endgroup\$
    – sai
    Commented Apr 8, 2023 at 2:13

1 Answer 1


Your problem is the add+ operator has higher precedence than the xor ^ operator. Put parentheses around the expression

probe_01 <= ( {a[1:0],a[31:2]} ^ {a[12:0],a[31:13]} ^ {a[21:0],a[31:22]} ) + b;

See Table 11-2—Operator precedence and associativity in the IEEE 1800-2017 SystemVerilog LRM


Your Answer

By clicking “Post Your Answer”, you agree to our terms of service and acknowledge you have read our privacy policy.

Not the answer you're looking for? Browse other questions tagged or ask your own question.