I'm designing a PCB for a Mancester decoder I simulated a while back (and also asked about here) (simulation on Falstad.com), and would like to include decoupling capacitors. I have no experience with them, and do not know to what extent they are needed when just using three 74HC00 chips, but I understand the theory behind them and want to apply it practically in the PCB to get some experience with them.

I assume the impedance over the ground plane, is lower than over the copper traces. Thus, the decoupling capacitor connection to the ground pin on the chip (pin 7, the chip is a 74HC00) could ideally have a longer distance than the connection to the VCC pin (pin 14) which is over a copper trace.

I thought I'd ask, if anyone has some good ideas about the conventions around this? For example, which of the three examples below would be best, or if there is in general ideal ways and conventions on how to connect a decoupling capacitor in this case.

I know "opinion based questions" are not popular on this SE, but my question aims to be about the theory about bypass capacitors, and the effect of different impedance in ground plane and copper traces. It just has an "opinion" aspect as a way to ask about that.

  • \$\begingroup\$ OK thanks! Then I have something to go by. \$\endgroup\$
    – BipedalJoe
    Commented Apr 9, 2023 at 12:50
  • \$\begingroup\$ For through hole parts where you inherently have a lot of lead inductance it usually isn't worth worrying too much about the exact position so long as it's physically close to the pins. \$\endgroup\$ Commented Apr 9, 2023 at 14:58
  • \$\begingroup\$ @user1850479 thanks! I went with placing them on the side, where the "U1" label is. But good point that it is not super exact. \$\endgroup\$
    – BipedalJoe
    Commented Apr 9, 2023 at 23:18

2 Answers 2


For example, which of the three examples below would be best, or if there is in general ideal ways and conventions on how to connect a decoupling capacitor in this case.

The left circuit is best because the ground connection is on a plane and it will always have a very low impedance between ground pin on the chip and ground pin on the capacitor hence, you seek to reduce the distance between Vcc pin on the chip and Vcc pin on the capacitor.

enter image description here


All of them are fine.

Shortest is best, but some length is tolerable. How much depends on the speed of the chip (output rise time) and load current.

There's also the option of putting the capacitor where the "U1" label is, which puts its GND pin closer to U1's (following the path of least inductance, which follows under the chip body). Note that, as shown, the ground plane is broken by the row of pins, so current can't flow directly between them and over from C2 to U1-7; instead it must flow around the edges of the slot. This is a tiny difference of course (<10nH?), but just to be complete.

There is also the option not listed, of using a wider/thicker trace. Very roughly speaking, doubling trace width halves inductance (which is true when width is much greater than PCB substrate thickness, and the effect is smaller when otherwise). At the low DC currents a logic gate is likely to be used at, trace width doesn't matter for thermal/ampacity purposes, but wider traces can still be used to reduce inductance a bit.

Inductance will be even lower with SMT components, which I recommend considering for use, as they aren't that much harder to place and solder, at least in the larger sizes (SOIC and 1206, say). Personally, I find TSSOP and 0603 easy enough to work with, with 0603 being a little slower to work with than 0805, and 0402 being quite a bit slower. But this does vary with ones' tactile practice and visual acuity.

So, for 74HC family with no particular loads, this is fine. The only thing in that family which would be a concern, is something like an octal bus driver with terminated load, in which case a short trace with a larger value cap might be desirable.

The cap can also be shared between neighboring chips. This is most acceptable when their currents aren't coincident, and least acceptable when all synchronized (so they all draw current pulses at the same time, such as from a common clock source or bus strobe). If you don't know better, safe to assume one cap per power pin.

As for other logic, note the dimension scales with rise time and current flow. So shorter traces are a higher priority for say 74LVC family logic, or STM32 microcontrollers, etc. Conversely, it's hardly a problem at all for CD4000 family logic, or vintage analog chips like LM324, LM393, µA7805, etc.

  • \$\begingroup\$ Thanks. Good point about that the chip pins are in the way of the current, and that placing the capacitor on the side might be better. Co-incidentally I ended up doing that before I read your answer (because it was better to put the chips side by side), but now I have even more reason for it. Will try soldering SMT this week, so might design something with it after that, but used THT for now since it is conceptually easier for me to start with. \$\endgroup\$
    – BipedalJoe
    Commented Apr 9, 2023 at 22:00

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