DAC DDR Interface with Vivado and Zynq7000

Question

i need to connect a dual-channel DAC (AD9117) to a Zynq 7000 FPGA. The DAC has a DDR Interface, on which the Data for Channel 1 is clocked on the rising edge and the data for channel 2 on the falling edge. The FPGA also has to provide the clock for this interface and it should be centeraligned to the DDR Data. That means the forwarded clock needs to have a 90 degree phase shift, with respect to the clock driving the oddrs. Now ive tried using the SelectIO Wizard to create such an interface but i cant change any clock/phase settings. Is there another wizard that allows me to do that or will i have to implement all of this manually?

Thank you!

Answer 1

In general, the clock you're sending to the DAC is handled as a logic signal inside the FPGA, not as a clock. You should use the same kind of ODDR module to drive it that you are using for the data lines.

The general idea is to use a single PLL or clock manager to generate two clocks inside the FPGA at the nominal clock rate, one delayed relative to the other by 90°. The first of these clocks will drive all of the ODDRs for the data, and the delayed clock will drive the ODDR for the external DAC clock signal. The data inputs to this last ODDR are simply tied low and high so that you get a square wave at this pin that has all of the same timing characteristics as the data pins, other than being delayed by the required amount.