This is [hopefully] the last question related to actuator signal capture. A short recap: we need to capture duty cycle, period and polarity of the bidirectional 24V ~20kHz signal from third party actuator controller with at least 1000 steps precision in the entire 0..100% range. The circuit is based on STM32G051 controller.

The problem of motor emulation kinda solved itself when we managed to disable open circuit detection in the actuator controller. I have solved the problem of capturing direction by adding D-trigger to one half of the signal and clocking it by positive edge of the PWM pulses. This works as expected, the last captured period and duty are available in the DMA buffers and the polarity of the last pulse is latched by the flip-flop.

The final problem is capturing the amplitude and the polarity of 0% and 100% input. When there are no pulses the last captured values getting stuck in the DMA buffers and D-trigger. Apparently I am not the first facing this problem, but the answers in questions like this are too generic to be useful.

Here is current circuit and corresponding signals: enter image description here enter image description here The idea is to somehow detect "no pulses" condition and generate Capture signal on OR gate to latch the input polarity in the flip-flop (come to think about it, I can drop the OR gate and connect OUT1 signal to GPIO to figure out the polarity and level of the input voltage without latching it).

First I tried TIM3 in One-pulse mode with slave reset and trigger by ITR0 from TIM1. This did not work since TIM1 was generating update event on every capture.

Then I tried TIM3 in PWM mode with slave reset by ITR0. Did not work either, probably for the same reason.

Finally I programmed TIM1 capture IRQ to write 1 into TIM3 counter, and TIM3 update IRQ to write 0 into PWM capture buffers. This works, but has some glitches and TIM3 IRQ is getting called even when there are incoming pulses, don't know why.

So, I am looking for suggestions for simple and reliable capture of 0% and 100% duty, preferably pure hardware configuration solution without any IRQ involved.


The terms 0% and 100% duty sound somewhat oksimoron-ish. What I really mean is one of the following three conditions: a) no current through A1 input, b) current flows from A1_1 to A1_2 and c) current flows from A1_2 to A1_1.

  • \$\begingroup\$ I'm struggling to see why OUT1 and OUT2 from U5 are not the pure inverse of each other. The inputs to U5 are commoned with one channel being inverted to the other hence, why OUT1 is not the pure inverse of OUT2 is baffling. \$\endgroup\$
    – Andy aka
    Apr 13, 2023 at 13:07
  • \$\begingroup\$ As I don't see any filters and you are triggering interrupts, I have to ask: Did you limit the speed somehow BTW, if your microcontroller is not super loaded, you can even trigger input interrupts and do what you have to do, I have seen some tachometers working with 10KHz signals like that. \$\endgroup\$
    – MF3
    Apr 13, 2023 at 15:32
  • 1
    \$\begingroup\$ @Andyaka the output of U5 isolator is low only when current flows from IN- to IN+. Since each input can be in 3 states (+, - and floating) there are 9 possible combinations, but only 2 of them result in 0 on one of the outputs. It is true that the wiring guarantees that they are never active at the same time, but it allows a third state when both are inactive. \$\endgroup\$
    – Maple
    Apr 13, 2023 at 15:43
  • \$\begingroup\$ @MF3 the isolator has some inherent hysteresis. According to oscilloscope the controller output does have substantial noise at the beginning of each pulse, but at 24V amplitude it is way above I-IL threshold. For these two reasons I did not think the filter is necessary. An oscilloscope on the outputs seems to confirm this. And after the NAND gate the only noise is gate's own logic switching. \$\endgroup\$
    – Maple
    Apr 13, 2023 at 16:22
  • \$\begingroup\$ @MF3 As for microcontroller, I am actually trying to avoid interrupts (as in IRQ handlers) and do everything on internal events. The MCU is rather slow and it has other things to do, besides PWM capture. Also, the beauty of the CC + DMA is that regardless of the input frequency the application can get ready results only when it needs them, which in my case is only about 20 times per second per channel. This is limited by the UART protocol which transfers captured data to where it is processed. \$\endgroup\$
    – Maple
    Apr 13, 2023 at 16:33

1 Answer 1


Capturing the source of the last pulse is a classic use for an SR (set/reset) type flip-flop. Since the pulses are negative, I'll use NAND gates:


simulate this circuit – Schematic created using CircuitLab

enter image description here enter image description here enter image description here

It sounds like you want to detect the absence of pulses, a task typically performed by the unsurprisingly named "missing pulse detector". Start by determining the longest duration you must wait before it's clear that pulses have stopped arriving. In your case, that's a little over \$\frac{1}{20kHz} = 50\mu s\$.

We can use a retriggerable monostable flip-flop, with a duration of, say 75μs. That's a piece of cake with the 74HC123:


simulate this circuit

As long as rising edges at PWM arrive quicker than 1 per 75μs or so, then the monostable is retriggered before it can time out, and its output \$\overline{Q}\$, node MISS, stays low. Otherwise it eventually times out (after 75μs), and MISS goes high, indicating that pulses have stopped.

  • \$\begingroup\$ Yes, the actual problem is exactly that - detect missing pulses and then analyze inputs to separate one of the 3 stable conditions: no voltage, DC in one direction or DC in the other direction. The idea to use external flip-flop is interesting. Technically, it is not much different from using internal timer resettable by pwm pulses, as I was trying to do. In my case it did not work because somehow timer was generating update IRQ even when software forcibly cleared its counter. This won't be a problem with external flip-flop. \$\endgroup\$
    – Maple
    Apr 19, 2023 at 17:01
  • \$\begingroup\$ Now, the use of SR flip-flop instead of D-type is very promising for capturing direction when pulses are present. D-type requires set-up time (provided by logic gates in my schematics) before clock pulse. SR does not, which makes it more reliable. Thanks for the idea! \$\endgroup\$
    – Maple
    Apr 19, 2023 at 17:05
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    \$\begingroup\$ I just realized one more thing. The SR also generates correct output with DC input (100% duty) in either direction. In the remaining case of no voltage (0% duty) the direction is irrelevant and can remain latched in any state. Wow! a simple change of flip-flop type simplified so many things. \$\endgroup\$
    – Maple
    Apr 20, 2023 at 14:49

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