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From what I know, CPU registers work with flip-flops and when the data must pass from one register to another it travels on a bus. This happens only through an appropriate control signal.

What I want to understand is what keeps the data locked in a flip-flop so as to make it travel on the bus only after authorization. The bit in the flip-flop can be 0 or 1, and at the end is an electrical signal

It occurs to me that there is something that works like a policeman who blocks traffic, in this case blocks the electrical signal, and when the control signal arrives he lets it pass on the bus to go to another register.

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Flip flops are often designed with a Clock Enable (CE) pin. When this pin is not asserted, the flip flop is "paused" and will not accept a new value on a clock edge. This is at least the "input" half of what you're asking.

As for the other side, that is, which signal ends up going to that flip flop, there are multiple historical methods. Older systems used busses where only one output could drive a shared line at a time, the other outputs would be "Tri-stated", making them appear as though they were disconnected by a switch. Look for a "Bus Transceiver" datasheet to see how this was managed in detail.

Modern systems however are not connected this way. Instead, signals are selected from using multiplexers, these are fundamental logic blocks that pass one of several inputs to an output. A multiplexer needs to have enough "control" signals to select any one of its inputs. For example, a multiplexer which can select one signal out of four (4-to-1) will need exactly two control inputs, while a 2-to-1 multiplexer needs only one control signal.

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