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I have designed the circuit shown below for a reference current of approximately 1mA and an output current of approximately 100uA. I have observed that I am able to supply approximately 100uA to load resistances up to ~50kOhm. Afterwards, the output current starts to drop significantly. I assume this is because of the voltage drop at collector terminal of the Q2 transistor due to increase in load resistance.

schematic

simulate this circuit – Schematic created using CircuitLab

I am trying to graph the output impedance of the current mirror versus the output current. I have calculated the output impedance of my circuit to be around 1.3MOhm (using Rout = ro[1+gm(RE//rpi)] ). I will assign parameter sweep to the degeneration resistance to vary the output current to see changes on output impedance. The load resistance will be kept constant at 1kOhm.

I can easily measure the output current but how can I measure the output impedance of my circuit in a simulator? I am using Tina-TI.

Edit: I obtained beta for Q2 as 70 regarding hfe/Ic curve in Onsemi datasheet for 2n3903. Va = 40.

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    \$\begingroup\$ The 50k load resistance limit is due to your 5V supply: 100uA x 50k = 5V. You can't have a current higher than what's given by U/R. That's your maximum resistance limit. \$\endgroup\$ Commented Apr 15, 2023 at 0:09

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What an interesting question!

You're right about the limited range of load resistance, and the reason for it, but I would explain it differently. I would say that the current sink stops working when Q2 becomes saturated, which occurs when the voltage drop across the load approaches the supply voltage. Slightly less, in fact, due to Q2's \$V_{CE(SAT)}=0.2V\$. That is:

$$ R_{LOAD(MAX)} = \frac{V_{SUPPLY} - V_{CE(SAT)}}{I_{LOAD}} \approx 50k\Omega $$

I don't know if the system for measuring output impedance that I describe below is what you're looking for, but it certainly permits you to plot a graph of output impedance vs. RE. Also, I'm not familiar with Tina, but I'm sure she's able to implement similar functionality.

schematic

simulate this circuit – Schematic created using CircuitLab

What I've done is create two nearly identical current mirrors, but in the second one I have modified the load resistance very slightly. This produces a slight difference in quiescent state, where the voltage across the sinks (Q2 and RE) has changed a tiny bit (\$\Delta V\$), and the current through them has also changed a tiny bit (\$\Delta I\$).

I have set the value of the two emitter resistors to parameter x, the value of which can be swept.

The dynamic impedance of the sink to ground will be the ratio \$\frac{\Delta V}{\Delta I}\$, as long as the change is very small. If I call Q2a's and Q2b's collector potentials \$V_A\$ and \$V_B\$, and their collector currents \$I_A\$ and \$I_B\$, the expression will be:

$$ R_{SINK} = \frac{V_A-V_B}{I_A-I_B} $$

This is what CircuitLab plotted for \$R_{SINK}\$ as x is swept from 100Ω to 700Ω:

enter image description here

Here's the sweep settings, and expression for \$R_{SINK}\$:

enter image description here

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    \$\begingroup\$ After I posted the question, I did some more research on course books related to electronics 2 courses. And you are right! The books generally speak of [dIo = dVce*(1/Rout)] and that is basically what you explained. Thank you very much for the clear explanation! \$\endgroup\$ Commented Apr 15, 2023 at 13:43

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