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I have a question about designing a stack up for a 4-layer PCB with a high-density top layer. I know the optimal way to generally do this is to go for either 1 or 2 as these stack ups provide a good return path.

(1)         (2)    (typical)

---sig/pwr--- --- GND --- --- sig ---

--- GND --- ---sig/pwr--- --- GND ---

--- GND --- ---sig/pwr--- --- pwr ---

---sig/pwr--- --- GND --- --- sig ---

However, the problem with figure 1 is that I can't route power or do a power pour on the top layer since, as I have said, there are too many components and signal traces, and the PCB can't be expanded.

Furthermore, figure 2 would cause the GND plane to get sliced up too much as a result of the components.

Is it OK to go with the typical stackup if I always place a return via (connected to GND) next to a via connecting the top and bottom signals? There will not be many vias connecting the top and bottom layers because the bottom of the PCB is pretty bare, but it must remain that way.

For reference, this is a low-speed DC circuit which I know means I could probably get away with simply going for the typical stack up, but I want to develop best practices to reduce EMI.

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    \$\begingroup\$ If it is a low speed DC circuit, what would produce EMI if it's a DC circuit? If you say you can use two GND layers, it sounds like the next question is why do you need a 4 layer board if you could go with basically 2 layers? \$\endgroup\$
    – Justme
    Apr 15, 2023 at 21:31
  • \$\begingroup\$ @Justme even though it is a low speed DC circuit, is it not still capable of producing some EMI? Sorry if that is a stupid question, I'm still new to this idea. Regardless, I'm just trying to develop best practices. Also, I think the board is too dense to route power/ pour power to make a 2 layer board, and although, there isn't much on the bottom layer, it would still be enough to split up a GND pour since the PCB is pretty small in area. \$\endgroup\$ Apr 15, 2023 at 21:40
  • \$\begingroup\$ You did not provide much info what is actually going on on the top layer. What mens dense to you, and what is a small board for you? Please quantify! For my precision analogue+MCU boards the "typical" stackup turned out the best option in most cases. My Boards are as small as 0.7 cm^2 up to 1 inch^2 and dense, often components on both sides too. \$\endgroup\$
    – datenheim
    Apr 15, 2023 at 22:15
  • \$\begingroup\$ @BradleyCampbell DC has no voltage or current changes, therefore it cannot produce EMI. And therefore it does not need a ground pour. On the other hand, you don't say what the circuit has or does so it may not be DC like you claim. \$\endgroup\$
    – Justme
    Apr 15, 2023 at 22:20
  • \$\begingroup\$ @Justme Sorry, what I think I meant is that it is a DC supply. The circuit is just a standard microcontroller with some sensors, so the signals are digital. \$\endgroup\$ Apr 15, 2023 at 22:56

2 Answers 2

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For reference, this is a low speed DC circuit which I know means I could probably get away with simply going for the typical stack up, but I want to develop best practices to reduce EMI.

What I'm describing below is required for high-speed circuits. It's probably not required for DC circuits. I'm writing this answer only because the O.P. is asking for best practices - in general.

What I wanted to know is if it is ok to go with the typical stackup if I always place a return via (connected to GND) next to a via connecting the top and bottom signals?

That would work for the options (1) and (2) stack-up, but not for the (typical) stack-up.
In the (typical) stack-up, the signals on the bottom layer are referenced to a ground plane, and the signals on the bottom layer are referenced to the power plane. A simple stitching via connected to GND can't simply connect to a power plane, because it would be a dead short power to ground. It's still possible to provide a high frequency return path if the stitching via is connected to GND, and the side of the via is connected to power plane through a capacitor.

That would be a lot of capacitors. That's why contemporary high speed designs rarely use power planes as reference planes. Speeds are getting higher, and PCB layers are getting cheaper.

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  • \$\begingroup\$ Thanks for the response, that definitely cleared some things up! However, since it doesn't seem feasible to put a power plane and signal traces on the same layer in my design, would I be able to make a 6 layer board where the stack-up was the following: (1) sig (2) GND (3) PWR (4) PWR (5) GND (6) sig? If I understand correctly, that would provide decent coupling between PWR and GND layers since they are close together, and the return paths for signal traces would always be above a reference plane which could be connected with vias if I needed to switch layers. \$\endgroup\$ Apr 15, 2023 at 22:14
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    \$\begingroup\$ @Bradley The 6 layer stack-up would work. You can also use layer (3) or (4) for signals which aren't sensitive to reference plane (LEDs, buttons, etc). You can run them on the same layer as power because you are using dedicated GND layers as reference planes. \$\endgroup\$ Apr 16, 2023 at 0:07
  • \$\begingroup\$ @Bradley Here's a thread about 6-layer stack-up. The O.P. over there is dealing with Ethernet signals which are high speed proper. \$\endgroup\$ Apr 21, 2023 at 3:03
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FYI, I've seen, on more than several occasions, users here insisting upon (1) over (typical). However, there are relatively few applications where that insistence bears fruit. For almost all commercial designs, (typical) is more than sufficient. It is, well... typical!

Don't worry about stitching the planes (at AC, i.e. by placing bypass caps (with vias) near signal vias): the fact that they are wide area and closely coupled has already solved this for you. A few bypasses scattered about will do the job; most likely you already have enough from local bypasses at chips.

If you need more routing area, there's always the option of a six-layer board. You can use the same VCC/GND (on Mid1 and Mid4 this time) and add two extra routing layers, or add planes if you prefer. (Or route within planes, assuming you have area for stitching vias.)

This general scheme (reserving about half of all layers as plane layers, while respecting symmetry*) applies to any number of layers, so you'll see PC motherboards made with, say, 8 layers, or server backplanes and other specialized stuff made with, heck, 32 or more layers, with about every other layer being a plane.

*Notice you can't** have three planes on a six-layer board while placing them symmetrically. Boards are laminated in layer or core pairs, so you want to use symmetrical dielectric and copper layers. So, you'd go for two or four planes in a six-layer board, as the preferred build.

**Well, shouldn't, really. Unbalanced copper density may lead to warpage (uneven shrinking as the freshly-bonded PCB cools to room temperature), making mechanical problems as well as poor soldering on dense SMT components. This mostly manifests over large boards (300mm+?), and egregious density mismatches (nearly empty layers vs. solid planes), I think? As long as you're making modest use of all layers, and the board isn't massive, don't worry about it, really.

When you need extraordinary performance (tight regulations say for mil/aerospace?), it may be worthwhile to sacrifice ease of layout, manufacture and debugging for a more internal-based design (outer pours plus many GND planes, routing power, or plane-ing power on additional layers as needed). Even so, it may happen that not enough advantage is had by such layout practices (e.g. RF that needs 80dB+ shielding, whereas the layout tricks might afford, say, 10-30dB?), and a shield can is required; or the shield can turns out cheaper anyway versus the extra board layers. At this point, it's merely options in the toolbox -- try them (project budget and time permitting, as always!) and see what works best.

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  • \$\begingroup\$ Thanks for the help! Yeah, I'm mainly trying to produce this board with "extraordinary performance" rather than just do enough to get by even if it would work fine which is why I'm so concerned about the layer stack-up. I don't know if you saw my comment above, but do you think a good alternative to figure (1) & (2) would be to go to a 6 layer board of the following stack-up: (1) SIG (2) GND (3) PWR (4) PWR (5) GND (6) SIG? This is symmetrical, great coupling between PWR & GND, and provides a good return path for transmission lines. I can also use a return via in this stack-up. \$\endgroup\$ Apr 15, 2023 at 23:11
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    \$\begingroup\$ If you have lots of power supplies, that would be fine. Two whole power planes seems like a lot, but I don't know what you're doing obviously. \$\endgroup\$ Apr 16, 2023 at 0:25

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