I have written this example to try to answer the question. There is one input, x, the clock, and three outputs. The clock pulses on and off, and x becomes 1 at random times for the positive edge of the clock.
The output should move the input of x from z1 to z3 with every clock pulse. For example, when x is equal to 1, three clock pulses in a row, the output should be 111. Similarly, if x is 1, 0, then 0, the outputs of z1, z2, and z3 should be 0, 0, and 1 respectively.
z1 works in my simulation. However, z2 and z3 remain constant at zero. It appears that the T flip-flop module does not change the value of q. However, I have simulated the flip-flop module by itself with no issue.
When I run the top level module, I get a warning message that t1, t0, q1, and q0 remain constant at zero. However, from the equations, t0 should become one the moment x becomes one, because of "t0 = ~q0&x + ..."
I have tried many variations of this code; putting the
always function in and around different sections of code, initiating and not initiating values for the t's and q's, defining the t's and q's as wires and or regs. I have also tried blocking and nonblocking variations on the equations, when inside
module TwoFFwithEquations( input x, input clk, output reg z1, output reg z2, output reg z3 ); reg t1, t0; wire q1, q0; initial begin t1 = 0; t0 = 0; end TFF tff1(t1, clk, q1); TFF tff0(t0, clk, q0); always@(posedge clk) begin t1 = q1&~q0 + ~q1&q0; t0 = ~q0&x + q0&~x; z1 = x; z2 = q0; z3 = q1; end endmodule
module TFF( input T, input clk, output reg Q ); initial begin Q = 0; end always@(posedge clk) begin case(T) 1'b0: Q<=Q; 1'b1: Q<=~Q; endcase end endmodule