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I've looked through this forum about PCB design of crystal oscillator and followed the tips, but I still not confident.

Any kind of feedback would be appreciated.

I put the 12 MHz crystal surrounded by a local GND plane and connected this plane to the the bottom uninterrupted GND plane through only one via.

Crystal Oscillator design

Adding manufacturer reference enter image description here

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  • \$\begingroup\$ Which MCU is that? Have you looked at MCU provided documentation? The single via to GND plane and the long loop from capacitors to the via sounds against most suggestions - it may still work just fine, but why bother isolating an area if it does not go via a noiseless route to MCU ground pin dedicated for crystal connections. \$\endgroup\$
    – Justme
    Apr 17, 2023 at 13:44
  • \$\begingroup\$ RP2040. I tried to follow the design suggest on the minimal hardware reference, but got in doubt about the vias. \$\endgroup\$ Apr 17, 2023 at 13:54
  • \$\begingroup\$ Those vias look explicit enough as to not create doubts so, what doubts did you have @GabrielGodoi and why did you have them? \$\endgroup\$
    – Andy aka
    Apr 17, 2023 at 15:40
  • \$\begingroup\$ @Andyaka my doubts is about what the information I got in this forum. Like electronics.stackexchange.com/questions/39136/… They contradicts \$\endgroup\$ Apr 17, 2023 at 16:11

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Splitting the GND plane is not a good idea, you should have one solid GND plane, on multiple layers. Consider what this split does to the current path from C9 and C6, it adds a pretty big loop that will result in inductance, degrading their performance, and potentially causing EMC issues. It also pinches the return path around C9 and D1, though I'd consider stitching these even if the plane was solid. Best practice is to have a Via on either side of a capacitor's pad. I cant pretend I do this 100% of the time, and it's not always practical, but I've drawn this for you here.
enter image description here If you get rid of the GND plane split I'd consider that a good layout, although I'd add a few more Vias to stitch the GND a bit better. It looks to me like the Xtal could move a smidge closer to U1, so you should do this unless you think it will give you assembly problems.

Also, as a very minor point, you could consider decreasing your thermal isolation, usually, I match this to my clearance, but this very much depends on how you're assembling these boards, and whether or not you feel this is needed to assemble the board well.

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  • \$\begingroup\$ I added the manufacturer reference I followed, could you enlight me about how this apply to the manufacturer reference? \$\endgroup\$ Apr 17, 2023 at 14:00
  • \$\begingroup\$ If splitting the plane is bad, then why do most MCU crystal application notes say that the crystal should have a separate ground plane connected to MCU ground pin with a single point? Not that it is necessary, but this answer contradicts what is the best practice. \$\endgroup\$
    – Justme
    Apr 17, 2023 at 14:13
  • \$\begingroup\$ @GabrielGodoi, in that image, the GND plane isn't actually split, there's a GND plane around the Xtal, and the surrounding pour is actually 3v3. The GND is well stitched, presumably to a pour on another layer. It doesn't look like a great layout to me, particularly that seems like a bad way to route the 3v3, but that's a bit beyond the scope of this question. \$\endgroup\$
    – LordTeddy
    Apr 17, 2023 at 14:51
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    \$\begingroup\$ @Justme There's a lot of poor information about handling GND planes out there, particularly in datasheets, IMO. Telling users to split GND planes to "prevent interference" is a common thing to see, and sort of makes sense in theory, but IMO is bad advice. The realities of splitting GND planes causes more problems than they solve. You might get separation of GND currents, but you create inductors/radiators like above. Best practice isn't necessarily found in datasheets. \$\endgroup\$
    – LordTeddy
    Apr 17, 2023 at 14:57
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    \$\begingroup\$ I just find it hard to believe that multi-million dollar companies would produce application notes how to best connect a crystal to their chips and they are all wrong. \$\endgroup\$
    – Justme
    Apr 17, 2023 at 14:59

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