For a project, I am trying to optimize my buck converter to obtain a power efficiency of 87 %. The non-optimized buck converter gives a power efficiency of 86 %.

I try to size my PMOS 'power' transistor, for example, to reduce the conduction loss, hence increasing the power efficiency. I have plotted the width (Wp) together with the number of fingers (PNOF) against the power efficiency. Result (simulated in cadence virtuoso) is seen in the figure below.

enter image description here

From this plot, I see that with different transistor widths in combination with the corresponding number of fingers, you will obtain the required power efficiency. However, if you want to minimize the chip area as well, do you use wider widths with less fingers for the PMOS power transistor or more fingers with less width? I am confused about it. Both of them seems achieve similar goal, but there should be a trade-off for when you opt for excessive fingers or too large widths (except increasing area).

Furthermore, this PMOS transistor (used in 180nm CMOS technology) is connected to Vin of 5V and serves as an example only. The main question to me is when do you opt for wider widths or more fingers for NMOS and/or PMOS 'power' transistors in synchronous buck converter?

With kind regards, Kwok

  • 2
    \$\begingroup\$ You could answer your immediate question just by plotting your transistor area against finger count and width. I'm not an IC designer, but if this is anything like board-level analog design the "absolute best" answer changes every time you change to a new technology or a new mix of senior engineers. \$\endgroup\$
    – TimWescott
    Apr 17 at 19:38
  • \$\begingroup\$ The transistor area is WLfingers of the transistor right? \$\endgroup\$
    – Kwok
    Apr 18 at 7:24

1 Answer 1


For your simulation, the only thing that really matters is width*PNOF.

Your 1st curve (90 μm; cyan) at 135 PNOF (total = 90*135 = 12150) has off = 86.7 %. Your last curve (150 um; purple) has the same efficiency at PNOF=80. This is the same effective size: 150*80 = 12000.

Similarly, look at peak efficiency —-- these are all the same value (87.7 %). Purple is 150 μm*120 = 18000; red is 120*150 = 18000, cyan = 90*200 = 18000.

There are differences in real layouts because of the metallization on the FET, but simple simulations won't show these.

For a given size (width & PNOF), plot efficiency vs. load current. This will be a parabolic shape. Adjust the FET size (either w or PNOF) so that the current at which peak efficiency occurs is the value you desire. With a given topology and technology it is not realistically possible to have efficiency higher than this achieves.

  • \$\begingroup\$ if you have given that the load current is 200 mA, but not given a range of that load current, then why would you still plot the efficiency vs load current? \$\endgroup\$
    – Kwok
    Apr 18 at 7:27

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