For a project, I am trying to optimize my buck converter to obtain a power efficiency of 87 %. The non-optimized buck converter gives a power efficiency of 86 %.
I try to size my PMOS 'power' transistor, for example, to reduce the conduction loss, hence increasing the power efficiency. I have plotted the width (Wp) together with the number of fingers (PNOF) against the power efficiency. Result (simulated in cadence virtuoso) is seen in the figure below.
From this plot, I see that with different transistor widths in combination with the corresponding number of fingers, you will obtain the required power efficiency. However, if you want to minimize the chip area as well, do you use wider widths with less fingers for the PMOS power transistor or more fingers with less width? I am confused about it. Both of them seems achieve similar goal, but there should be a trade-off for when you opt for excessive fingers or too large widths (except increasing area).
Furthermore, this PMOS transistor (used in 180nm CMOS technology) is connected to Vin of 5V and serves as an example only. The main question to me is when do you opt for wider widths or more fingers for NMOS and/or PMOS 'power' transistors in synchronous buck converter?
With kind regards, Kwok