I am re-learning electronics basics (starting with the JFET). After going through several JFET datasheets (2N548x, 2N545x, J11x, J310 etc) I found it hard to map the theoretical aspects to the the practical aspects of the datasheet and have few questions -

  1. While the limits of a JFET are typically drawn in the Vds vs Id curve, the datasheet defines the limit in terms of Vdg and Vgs - Why? Why not in terms of Vgs and Vds? Is it because when biasing the amplifier Vdg is more commonly encountered in design?

  2. The pinch of voltage Vgs(off) seems to have a high range even for a specific chip (Eg - -0.3V to -3.0V for 2N5484). The same goes with Idss (Eg - 1mA to 5mA for 2N5484).

    1. With such a high variance how does one design amplifier type circuits for mass manufacture (since Q-point depends on Vp and Idss)?

    2. What would be a good way / circuit to precisely determine Vp or Vgs(off) for a chip at hand?

  3. All values which are theoretically constant (Idss, Vp) are defined against a particular Vds (Vds = 15V for 2N5484) - Why? Is this because Idss slightly varies with Vds even in saturation region?

  4. What is Igss (Gate reverse current)? What is its practical significance?

EDIT: Reference data sheet : 2N548x

  • \$\begingroup\$ Please link the data sheet you refer to and please mention the page number of the graph that is the basis of your question. \$\endgroup\$
    – Andy aka
    Apr 19 at 19:25
  • \$\begingroup\$ James Fiore has an excellent Creative Commons licensed textbook called Semiconductor Devices: Application & Theory that you can download for free. [www2.mvcc.edu/users/faculty/jfiore/freebooks.html] Chapter 10 covers the JFET and discusses a few options for biasing. In short, some biasing methods are more affected by variation in device parameters than others. In the textbook you will find graphs showing how the operating point of each biasing circuit will change, and by how much, based on manufacturing variances. \$\endgroup\$
    – Dave H.
    Apr 19 at 19:59

1 Answer 1

  1. JFETs are symmetrical devices*. There is no overlap between D and S directly, but they are separated by G. So it doesn't make much sense to specify D-S (or S-D).

*Well, surviving Si types are. And, maybe not completely symmetrical, but not dramatically so either. Like, 20 vs. 40V D-G and S-G or something. There are SiC JFETs available today, for power switching purposes, which are quite asymmetrical: 10 or 20V S-G, >600V D-G.

  1. The same way we do for any other transistor. Note that BJT VBE isn't reliable; it's quite consistent for a given part, but varies modestly between parts, and most importantly, varies dramatically with temperature. In a single-transistor common-emitter amplifier for example, base voltage is fixed (by a voltage divider, say) and emitter voltage is allowed to vary, with emitter current fixed by a resistor. Thus the bias current varies by only the spread of VBE relative to the total emitter resistor voltage drop.

    JFETs can be matched by buying them that way, or setting up in a circuit with a useful drain voltage (say 5-15V), fixed gate voltage (say 0V), and a constant current from the source (say 50uA) to a negative supply. The G-S voltage is then the pinch-off voltage (when the current equals the test current for that parameter).

    If you were curious about why, the reason is that the channels formed between D-S, through the G layer, are extremely thin, formed by the diffusion of dopants into the silicon. While the doping impurities don't move very quickly during manufacture, the distance scale is very small, and the levels are very precise (local concentrations of parts per trillion make all the difference). So it's very difficult to control. Newer types, like BF862 (now obsolete) or CPH3910, as well as offering optimized performance (high gm, medium IDSS, and low capacitance), offer tighter parameter spread. (I don't know offhand if that's due to better process optimization, or alternative technology (epitaxy instead of diffused).)

  2. High enough not to matter, i.e. avoiding the triode region.

  3. Its practical significance is significant! The gate junction is a (normally reverse biased) diode, so can have quite low input current, whereas a BJT incurs full base current (Ic / hFE). This makes JFETs excellent choices for high impedance amplifiers, electrometers, voltage buffers, etc.

    It's noteworthy that IGSS generally increases at high VDS, due to hot-carrier effects I think (basically, the current flowing through the pinched (saturated) channel, can flow so "fast" that some electrons (or holes) tunnel out of the channel and fall into the gate). For least gate current, this voltage should be kept modest.

    By extension, JFETs can also be used as low-leakage diodes. G and D+S are oppositely doped silicon, so if you tie D+S together, you simply get a diode from G to them. Not a good one, mind -- the internal resistance is comparable to the channel resistance, and maximum current is limited (IG(max) might be 10mA). But within that range, the leakage current can be much smaller than say 1N4148.


Your Answer

By clicking “Post Your Answer”, you agree to our terms of service and acknowledge that you have read and understand our privacy policy and code of conduct.

Not the answer you're looking for? Browse other questions tagged or ask your own question.