I am re-learning electronics basics (starting with the JFET). After going through several JFET datasheets (2N548x, 2N545x, J11x, J310 etc) I found it hard to map the theoretical aspects to the the practical aspects of the datasheet and have few questions -
While the limits of a JFET are typically drawn in the Vds vs Id curve, the datasheet defines the limit in terms of Vdg and Vgs - Why? Why not in terms of Vgs and Vds? Is it because when biasing the amplifier Vdg is more commonly encountered in design?
The pinch of voltage Vgs(off) seems to have a high range even for a specific chip (Eg - -0.3V to -3.0V for 2N5484). The same goes with Idss (Eg - 1mA to 5mA for 2N5484).
With such a high variance how does one design amplifier type circuits for mass manufacture (since Q-point depends on Vp and Idss)?
What would be a good way / circuit to precisely determine Vp or Vgs(off) for a chip at hand?
All values which are theoretically constant (Idss, Vp) are defined against a particular Vds (Vds = 15V for 2N5484) - Why? Is this because Idss slightly varies with Vds even in saturation region?
What is Igss (Gate reverse current)? What is its practical significance?
EDIT: Reference data sheet : 2N548x