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I have a couple of questions about the stack up and routing strategy in a 6 layer PCB.

I'm in the situation where all the important chips are on the top layer, so all the important tracks start and end on the top layer. In this situation which stack up is better:

Option A:       
1 - Signal;
2 - GND;
3 - Signal;
4 - Power;
5 - GND;
6 – Signal;

Option B:       
1 - Signal;
2 - GND;
3 - Power;
4 - Signal;
5 - GND;
6 – Signal;

That is, is it better to have the Power plane closer to the top layer (where the important chips are) or closer to the bottom layer?

The second question is about routing:

I'll try to explain myself with a practical situation: to connect my Ethernet controller I have to use two signal layers, let's imagine just as an example having the stack up of option A; As two signal layers, it is better to use the top layer and the inner signal layer, or it is better to use the top layer and the bottom layer?

My doubt arises from the fact that in the first case I would have the advantage of having two layers that have the same ground plane as a reference, but the vias act as stubs. In the second case instead, I wouldn't have the stubs of the vias, but I would use two layers that have different reference planes; so, I guess I should put several stitching away.

Which two layers are the most suitable?

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  • \$\begingroup\$ You would route power as traces, rather than using a plane..? And, does it need to be 6 layers at all? \$\endgroup\$ Commented Apr 19, 2023 at 23:12
  • \$\begingroup\$ Note that highly simplified questions such as this, necessitate equally simplified, generic rule-of-thumb, seemingly dogmatic answers -- a meaningful reply is either generally applicable and so long as to be meaningless to the novice; or is brief enough to apply, but inscrutable in its reasoning (i.e. it must be taken as fact; dogma), and so will necessarily be misunderstood and misapplied. How much that misapplication costs, depends. It might be utterly inconsequential, or it might be added weeks in the EMC test lab. \$\endgroup\$ Commented Apr 19, 2023 at 23:16

2 Answers 2

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With only the limited info you provide, a generic answer for having impedance controlled traces on a 6 layer board is usually that you use layers 1 and 6 for the impedance controlled traces and layers 2 and 5 as ground planes for them. The power layer being 3 or 4 does not matter much but use 3 if you want it marginally closer to important chips.

That means that when designing the PCB stack-up, you need to be most careful with the two sheets that have layers 1-2 and 5-6.

While vias are potential problems in the signal path, they can be designed to have a specific impedance you need, and because these impedance controlled vias go from top to bottom layer only, the vias are not stubs.

The problem of switching the reference plane can simply be handled by having ground vias between layers 2 and 5 near the signal vias that go between layers 1 and 6.

In some cases you could also use a 4 layer board with ground plane as reference for one layer and supply plane as reference for the other layer. The reference planes just can't be directly stitched together with vias but they can be coupled together with capacitors.

The problem of having impedance controlled signals on layers 1 and 3 with ground and supply/ground on layers 2 and 4 is that the signals on layer 3 need to be designed as having both layers 2 and 4 as reference and controlling impedance of layers 2 and 3 is more difficult that layers 1 and 2 that is a single sheet. Therefore signals on layer 3 must have different geometry than layer 1 signals.

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... to connect my Ethernet controller I have to use two signal layers. Let's imagine just as an example having the stack up of option A. As two signal layers, it is better to use the top layer and the inner signal layer, or it is better to use the top layer and the bottom layer?

Signal integrity will be better if both signals are referenced to the same plane. Layer 1 and layer 3 are a better option than layer 1 and layer 6.

... I would have the advantage of having two layers that have the same ground plane as a reference, but the vias act as stubs.

The advantage that the signal layers 1 and 3 are referenced to the same plane outweigh the stubs caused by vias. For example, there are DDR interfaces laid out in layer 1 and 3, and they have common throughole vias (no blind vias, no back drilling).
Thus - option A.

1 - Signal
2 - GND plane
3 - Signal
4 - Power
5 - GND plane
6 – Signal;

Another approach is to "treat power as signal" and use both layers 3 and 4 for both power and signal, depending on local convenience.

update:

[from a comment ]
Do I have to insert also the power plane as reference or just the ground plane on layer 3 ?
I.e. are the traces on layer 3 microstrip or stripline?
I ask because the width of the traces necessary to have 50ohm is very different in the two cases.

Ideally, you'd use only ground as reference plane(s). Ideally, you wouldn't use both power and ground as a reference planes at the same time, because the will be impedance between power and ground plane. If you chase that ideal, you'd have to add a pair of ground planes to the board, so you'd get an 8-layer board.

I'll make a working assumption that you want to stick with an 6-layer board. There's a compromise - the thicknesses of the dielectric don't have to be equal. If the signal layer is closer to the ground plane than to the power plane, then the ground will act as a reference plane for the most part. If we insert the dielectric thicknesses, then a 6-layer stack-up could look approximately like this:

1 - Signal
      0.005" [0.13mm] dielectric
2 - GND plane
      0.005" [0.13mm] dielectric   // this is the smaller distance between the signal layer and the GND plane
3 - Signal
      0.040" [1mm] dielectric      // this is the larger distance between the signal layer and the power plane
4 - Power
      0.005" [0.13mm] dielectric   // same symmetrical thing on the other side of the PCB
5 - GND plane
      0.005" [0.13mm] dielectric
6 – Signal

Check with your PCB fab what their default 6-layer stack-up is. If the default is not the stack-up you need, then ask them how much they charge for a non-default stack-up. Then it becomes a question of micro-economics: 6-leyer or 8-layer, prototyping or mass production.

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  • \$\begingroup\$ ok, so option A with the traces on layer 1 and layer 3. At this point I have a question, but to calculate the impedance in the filed solver, for the traces on layer 3 I have to insert also the power plane as reference or just the ground plane on layer 3? I.e. are the traces on layer 3 microstrip or stripline? I ask because the width of the traces necessary to have 50ohm is very different in the two cases. \$\endgroup\$ Commented Apr 20, 2023 at 19:04
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    \$\begingroup\$ @FedericoMassimi For a generic case, that's the reason you would route the impedance controlled lines on layers 1 and 6 and have ground planes for them on layers 2 and 5. \$\endgroup\$
    – Justme
    Commented Apr 21, 2023 at 18:04

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