As you already know, the 74LCX245 is bidirectional, but the direction has to be configured with a pin. So the I2C master would need logic to toggle the pin from transmit to receive whenever it is done talking, so that it can receive the acknowledgement. Since you're not implementing the I2C control block, but just using one, and it does not expose the signals which indicate the transmit/receive transitions, driving this transmit/receive pin will be difficult, but it is not provably impossible.
Therefore, the answer to your question can I still use it? is yes, I think. You'd need a circuit which tries to guess when the master is in a transmit state. This might be done by monitoring SDA and SCL to detect the passage of the start and stop conditions which basically indicate that the master is taking the bus and releasing the bus. When the master wants to speak, it will first pull SDA low. Basically, at the point it seems like a good idea to immediately put the 74LCX245 into transmit. What's coming next is the clock edge transition which indicates the start. But you don't want to delay the passage of the SDA pull down, so that the slave devices get a clear start condition. Then later if you see SDA going high while the clock is also high, that's a stop condition, and the chip can be flipped to receive.
One problem is that the chip has a just single global pin for flipping direction of all of its lines. You don't want to change the direction of the SCL line, which always goes from master to slaves. You never want to throttle the clock, even for a moment. So if you insist on using nothing but the 74LCX245, you will need two of them.
Another consideration is that the chip does not have open-drain outputs, but rather buffered ones. This could present a problem in two ways:
When the 74LXC245 drives its output low, the output will be expected to sink the current from the pull-down resistors on the bus. Luckily, this is fine since the datasheet lists ±50mA as the maximum output sourcing or sinking current.
A problem occurs if the 74LXC245 is configured to transmit and drives a high state onto the bus, while it so happens that a device pulls down the bus, also trying to transmit. The transmitter's buffer is then feeding current directly into the device's drain, which is nearly shorted to ground. Perhaps some small resistor could defend against this: large enough to limit current, but small enough that the logic level can be pulled down sufficiently close to zero (since that resistor will pair with the pull-down resistor on the bus to form the bottom of a voltage divider).
In regard to the previous point, you should probably make use of the global disable which puts both sides into high-Z. I.e. determine when the bus is completely idle and turn off the chip. Prior to detecting when the master wants to transmit, the chip should not be in receive mode because then it could drive the master's drain. Ideally you want the chip in bilateral high-Z mode, and from there, go to transmit. Then to receive (for the reply fro the device) and then back to high-Z.