5V, 50 Ω input single pulse signal to an FPGA

Question

I have a 5 V, 50 Ω input single pulse signal (<1 ms pulse width) going into Trenz TE0711 (operating @3.3 V and 50 MHz clock). Since the input signal is too high of a voltage, I am trying to find a way to reduce the voltage and keep jitter low (<1 ns). I also want it to be dummy proof where if someone puts in a high-voltage signal or an AC signal it doesn't fry the FPGA. I am not familiar with analog electronics, so I apologize if this is a simple question.

Currently, I am thinking of having a 3 V zener diode to act as a regulator and use a current limiting resistor (250 Ω) in front. However, I am not familiar with other components that may be out there that could meet my needs. I am concerned that zener diodes may have high jitter, but I just don't know. I am also worried if the 250 Ω resistor will cause a mismatch with the 50 Ω input signal and cause reflections.

Lastly, what would be the best way to test this? Could I use a delay/pulse generator and generate a 5 V, 50 Ω single shot pulse and just connect it directly onto my circuit that is on a breadboard and hook up an oscilloscope? Or, are there other ways to ensure proper and precise measurements?

Answer 1

You have a 5 V signal that must go into a 50R termination resistance. You can use the below circuit. This reduces the 5 V to approx. 2.7 V, well above the 2.0 V min. for an LVTTL input HIGH and above the 2.3 V min (70% of 3.3 V) for LVCMOS.

Configure your FPGA input pin to be a Schmitt trigger, if it can. That will use an even lower logic HIGH threshold voltage.

^{simulate this circuit – Schematic created using CircuitLab}

D1 protects the FPGA input pin from overvoltages by clamping the input to 0.3 V above the supply rail. D2 protects it against undervoltages by clamping it to 0.3 V below GND. Current limit resistor R3 reduces the overvoltage/undervoltage current to a safe level. You can modify the R3 value to suit the voltages it could be subject to. R2 will already load transients and dissipate them so it's continuous overvoltages that are the concern. When driven by a cable, it's a good idea.

A propagation delay is produced by R3, the capacitance of D1, D2 and the FPGA input pin, along with the tracking impedance. If this threatens your low jitter requirement, you can go without R3, D1 and D2.