I have a 5 V, 50 Ω input single pulse signal (<1 ms pulse width) going into Trenz TE0711 (operating @3.3 V and 50 MHz clock). Since the input signal is too high of a voltage, I am trying to find a way to reduce the voltage and keep jitter low (<1 ns). I also want it to be dummy proof where if someone puts in a high-voltage signal or an AC signal it doesn't fry the FPGA. I am not familiar with analog electronics, so I apologize if this is a simple question.

Currently, I am thinking of having a 3 V zener diode to act as a regulator and use a current limiting resistor (250 Ω) in front. However, I am not familiar with other components that may be out there that could meet my needs. I am concerned that zener diodes may have high jitter, but I just don't know. I am also worried if the 250 Ω resistor will cause a mismatch with the 50 Ω input signal and cause reflections.

Lastly, what would be the best way to test this? Could I use a delay/pulse generator and generate a 5 V, 50 Ω single shot pulse and just connect it directly onto my circuit that is on a breadboard and hook up an oscilloscope? Or, are there other ways to ensure proper and precise measurements?

  • \$\begingroup\$ What are the rise and fall times of the input signal? You need this information to determine if you will have an issue with reflections. \$\endgroup\$
    – The Photon
    Commented Apr 24, 2023 at 15:39
  • \$\begingroup\$ Also consider a buffer or inverter front-end to the FPGA pin. You want the edge to be clean and fast regardless of whatever the user inputs. Perhaps one with hysteresis also - might "take care of" minor line noise. \$\endgroup\$
    – rdtsc
    Commented Apr 24, 2023 at 15:51
  • \$\begingroup\$ @ThePhoton The rise and fall times of the input signal vary depending on what device is used. It can be <750ps or 2-3ns. Also, the pulse width is <1ms. \$\endgroup\$
    – trident_
    Commented Apr 24, 2023 at 16:10
  • \$\begingroup\$ @rdtsc Would a level shifter from 5V to 3V for this instead of a zener be more appropriate for this problem? \$\endgroup\$
    – trident_
    Commented Apr 24, 2023 at 16:20
  • \$\begingroup\$ From where does the 5V signal come from, and does it have 50 ohm source impedance? If so, after 50 ohm termination, the pulse amplitude is 2.5V. \$\endgroup\$
    – Justme
    Commented Apr 24, 2023 at 17:40

1 Answer 1


You have a 5 V signal that must go into a 50R termination resistance. You can use the below circuit. This reduces the 5 V to approx. 2.7 V, well above the 2.0 V min. for an LVTTL input HIGH and above the 2.3 V min (70% of 3.3 V) for LVCMOS.

Configure your FPGA input pin to be a Schmitt trigger, if it can. That will use an even lower logic HIGH threshold voltage.


simulate this circuit – Schematic created using CircuitLab

D1 protects the FPGA input pin from overvoltages by clamping the input to 0.3 V above the supply rail. D2 protects it against undervoltages by clamping it to 0.3 V below GND. Current limit resistor R3 reduces the overvoltage/undervoltage current to a safe level. You can modify the R3 value to suit the voltages it could be subject to. R2 will already load transients and dissipate them so it's continuous overvoltages that are the concern. When driven by a cable, it's a good idea.

A propagation delay is produced by R3, the capacitance of D1, D2 and the FPGA input pin, along with the tracking impedance. If this threatens your low jitter requirement, you can go without R3, D1 and D2.

  • 1
    \$\begingroup\$ Thank you, I will try this and let you know how it goes! \$\endgroup\$
    – trident_
    Commented Apr 25, 2023 at 15:33
  • \$\begingroup\$ Built on breadboard and connected it to a DG535 and a Tektronix scope (3.25GS/s sample rate). I took a delay measurement between the input and output and looked at the variance (jitter) and got ~600 ps. I am wondering if my jitter measurement is accurate as I was using a standard breadboard and am worried that I may have noise/interference through the contacts and capacitance within the breadboard. Would it be better to make the jitter measurement by implementing the above circuit on a prototype PCB board? I ask this as this a subcircuit within an entire system that must have a jitter <1 ns. \$\endgroup\$
    – trident_
    Commented May 19, 2023 at 15:30
  • \$\begingroup\$ @trident_, I think it's asking too much to get such a tight jitter requirement out of a breadboard circuit, particularly over time and if you're planning to make more. A PCB with decent tracking impedances and a ground plane will certainly improve things but that also depends on the rest of the system circuit you have. \$\endgroup\$
    – TonyM
    Commented May 19, 2023 at 16:31
  • \$\begingroup\$ Alright, I think I should also get a hold of a better oscilloscope with higher resolution since the resolution of the current scope is ~300 ps. So, the jitter variance is really a variance of 2 samples, which is probably not ideal by any means. \$\endgroup\$
    – trident_
    Commented May 19, 2023 at 16:36
  • \$\begingroup\$ I did some AC tests and put a 5V AC signal in and got -0.7 V across the FPGA on the -V part of the AC signal. The concern I have is the FPGa datasheet lists the minimum voltage as being -0.4V which exceeds the minimum spec on the datasheet. Also, if I put in a 9 V AC signal, I end up with nearly 5 V across the FPGA, which exceeds the maximum voltage of the FPGA datasheet. Is a zener circuit worth doing instead? \$\endgroup\$
    – trident_
    Commented May 22, 2023 at 21:40

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service and acknowledge you have read our privacy policy.

Not the answer you're looking for? Browse other questions tagged or ask your own question.