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For I2C communication following statement supposed to be true:

"One data bit is transferred during each clock pulse of the SCL."

I was reading here and in Figure 7, and with confusion something does not fit in the statement above.

To ask the question clearly, in the following diagram I marked some points(x, y, z) at the beginning of SDA in Figure 7 in red color where data bits change(only where bits alternate):

enter image description here

My question is:

At time x, y and z the SDA data bits change when the master is sending data. But these data bit changes are neither aligned with SCL rising edges nor with SCL falling edges. So by looking at the diagram I cannot verify the statement "One data bit is transferred during each clock pulse of the SCL". Why do data bit changes not happen at clock rising or falling edges but somewhere in between. Is this diagram wrong or am I interpreting something wrong here?

I though at each clock rising or falling edge the master would output a new bit. I hope my question is clear.

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3 Answers 3

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One data bit is transferred per clock pulse. The statement is true and apparent from the picture.

But the data has to be set up and be stable some time before the rising clock edge, and must be held stable for some time after the falling clock edge, as data is allowed to change only during when clock is low.

So in short, what you see is perfectly correct on an simplified I2C diagram that the data wire is updated with a new bit at the middle point of clock line being low.

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In I2C, the master always supplies the clock, and when writing, the data.

The SDA line is sampled by the device some time when the SCL line is high. As in, the device will read 1 if the data line is high during a clock pulse, and 0 if it's low at that time.

To reliably transfer data, the data line has to be stable and not in some "in-between-value" when it is measured. This is why the transitions on the data line will be skewed compared to the clock line, and why the spec says that SDA can only change when the clock line is low.

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  • \$\begingroup\$ “…when clock line toggles…” is incorrect. Only one bit per SCL pulse, not two. \$\endgroup\$
    – RussellH
    Apr 25, 2023 at 15:58
  • \$\begingroup\$ @RussellH True, edited to (hopefully) clarify. \$\endgroup\$
    – Araho
    Apr 25, 2023 at 20:32
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"One data bit is transferred during each clock pulse of the SCL."

I'd be careful with that statement. Correct would be:

A bit is sampled as the state of SDA on the rising edge of SCL

While SCL is pulled low, what happens on SDA doesn't matter. While it's pulled high, you're not allowed to change the state of SDA. Aside to signal framing!

So, I'd say your statement is wrong: while there can only be one bit per clock cycle (because there's by definition only one rising edge per clock cycle), the inverse isn't true, necessarily.

at the beginning of SDA

SDA is a signal. It has no beginning and no end. Its edges do not matter. What matters is its state when SCL gets pulled high.

your x markers are irrelevant points in time.

I²C is not an UART bus. There's a clock line, SCL. You need to interpret the data line at the times given by the edges of that line!

I though at each clock rising or falling edge the master would output a new bit.

It is, but the clock line is SCL ("Serial CLock), not SDA (Serial DAta).

And also, the master is the one who's generating the rising edges of SCL. It's not the only one sending data!

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  • \$\begingroup\$ Justme is correct, One bit per pulse regardless of when sampling occurs. Any change of SDA while SCL is high will be interpreted as start, repeated start or stop \$\endgroup\$
    – RussellH
    Apr 25, 2023 at 15:51

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