For I2C communication following statement supposed to be true:
"One data bit is transferred during each clock pulse of the SCL."
I was reading here and in Figure 7, and with confusion something does not fit in the statement above.
To ask the question clearly, in the following diagram I marked some points(x, y, z) at the beginning of SDA in Figure 7 in red color where data bits change(only where bits alternate):
My question is:
At time x, y and z the SDA data bits change when the master is sending data. But these data bit changes are neither aligned with SCL rising edges nor with SCL falling edges. So by looking at the diagram I cannot verify the statement "One data bit is transferred during each clock pulse of the SCL". Why do data bit changes not happen at clock rising or falling edges but somewhere in between. Is this diagram wrong or am I interpreting something wrong here?
I though at each clock rising or falling edge the master would output a new bit. I hope my question is clear.